usb: dwc3: Add SoftReset PHY synchonization delay

[ Upstream commit fab3833338779e1e668bd58d1f76d601657304b8 ]

>From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index b8d272ed2355e3f8b9f05d28d75dfe513b97b380..53b26e978d90e566a0cc4f13a461b28665ce2bd3 100644 (file)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -161,7 +161,7 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
        do {
                reg = dwc3_readl(dwc->regs, DWC3_DCTL);
                if (!(reg & DWC3_DCTL_CSFTRST))
-                       return 0;
+                       goto done;
 
                udelay(1);
        } while (--retries);
@@ -170,6 +170,17 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
        phy_exit(dwc->usb2_generic_phy);
 
        return -ETIMEDOUT;
+
+done:
+       /*
+        * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
+        * we must wait at least 50ms before accessing the PHY domain
+        * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
+        */
+       if (dwc3_is_usb31(dwc))
+               msleep(50);
+
+       return 0;
 }
 
 /**