drm/i915/dsi: Using the bpp value wrt the pixel format

The bpp value which is used while calulating the txbyteclkhs values
should be wrt the pixel format value. Currently bpp is coming
from pipe config to calculate txbyteclkhs. Fix it in this patch.

V2: dsi_pixel_format_bpp is used to retrieve the bpp from pixel_format
	[Review: Jani]

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Tested-by: Mika Kahola <mika.kahola@intel.com> # BYT
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455203007-10850-1-git-send-email-ramalingam.c@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b928c503df24dd6c43d6926afca62b3dff703912..01b8e9f4c2726ecd242005643f4e80de687afaee 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -785,10 +785,9 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 {
        struct drm_device *dev = encoder->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
        struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
        enum port port;
-       unsigned int bpp = intel_crtc->config->pipe_bpp;
+       unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
        unsigned int lane_count = intel_dsi->lane_count;
 
        u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
@@ -859,7 +858,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
        struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
        const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
        enum port port;
-       unsigned int bpp = intel_crtc->config->pipe_bpp;
+       unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
        u32 val, tmp;
        u16 mode_hdisplay;
 

diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index de7be7f3fb42c8167fa4c9b677de4c163750c64e..92f39227b3610761382d78c1b25a99c9f63cc0b8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,8 @@
 #define DSI_DUAL_LINK_FRONT_BACK       1
 #define DSI_DUAL_LINK_PIXEL_ALT                2
 
+int dsi_pixel_format_bpp(int pixel_format);
+
 struct intel_dsi_host;
 
 struct intel_dsi {

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 787f01c63984e574fa038d3cbed09481053e3e40..7f145b4fec6a1c96ca36a7f7edabac22b7d280d4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -440,10 +440,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
        intel_dsi->dual_link = mipi_config->dual_link;
        intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 
-       if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
-               bits_per_pixel = 18;
-       else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
-               bits_per_pixel = 16;
+       bits_per_pixel = dsi_pixel_format_bpp(intel_dsi->pixel_format);
 
        intel_dsi->operation_mode = mipi_config->is_cmd_mode;
        intel_dsi->video_mode_format = mipi_config->video_transfer_mode;

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index bb5e95a1a4530812809c06bded3492e7547c73a8..70883c54cb0a5ad84d44a7cc2fd7f79bf46717b5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -30,7 +30,7 @@
 #include "i915_drv.h"
 #include "intel_dsi.h"
 
-static int dsi_pixel_format_bpp(int pixel_format)
+int dsi_pixel_format_bpp(int pixel_format)
 {
        int bpp;