drm/amd/powerplay: fix typo error when set clock gate state.
authorRex Zhu <Rex.Zhu@amd.com>
Wed, 20 Jul 2016 10:13:47 +0000 (18:13 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 29 Jul 2016 18:36:59 +0000 (14:36 -0400)
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c

index e1b649bd5344919b55786bea9fd5fd49c48e240b..5afe82068b29b3b8c1a8443056f2e2db4b4699d5 100644 (file)
@@ -56,7 +56,7 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
                fiji_update_uvd_dpm(hwmgr, false);
                cgs_set_clockgating_state(hwmgr->device,
                                          AMD_IP_BLOCK_TYPE_UVD,
-                                         AMD_PG_STATE_UNGATE);
+                                         AMD_CG_STATE_UNGATE);
        }
 
        return 0;
index aeec25c66aa83ed5600981b3456cad076d9a7166..423ab6348d3d6299443fc95527133a51b20cb25b 100644 (file)
@@ -116,7 +116,7 @@ int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
                polaris10_update_uvd_dpm(hwmgr, false);
                cgs_set_clockgating_state(hwmgr->device,
                                AMD_IP_BLOCK_TYPE_UVD,
-                               AMD_PG_STATE_UNGATE);
+                               AMD_CG_STATE_UNGATE);
        }
 
        return 0;