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drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Tue, 7 Jun 2016 14:19:12 +0000 (17:19 +0300)
committerMika Kuoppala <mika.kuoppala@intel.com>
Fri, 15 Jul 2016 12:51:27 +0000 (15:51 +0300)
This is needed for all kbl revision.

v2: Don't add revid checks to generic gen9 init (Arun)

References: HSD#2135593
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-21-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 954337aa96a31f6d4baf1e40ac219fbb1b1d92f4)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
drivers/gpu/drm/i915/intel_ringbuffer.c patch | blob | blame | history

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a88ac279038556e84ab16001b3fd4d33a912ceb8..279614c70fe20164dd2db6c95b641b429127a2af 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1233,6 +1233,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
        /* WaDisableGafsUnitClkGating:kbl */
        WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
+       /* WaDisableSbeCacheDispatchPortSharing:kbl */
+       WA_SET_BIT_MASKED(
+               GEN7_HALF_SLICE_CHICKEN1,
+               GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
        /* WaDisableLSQCROPERFforOCL:kbl */
        ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
        if (ret)