trace_i915_gem_ring_sync_to(to, from);
if (!i915.semaphores) {
- ret = i915_wait_request(from,
- I915_WAIT_INTERRUPTIBLE |
- I915_WAIT_LOCKED,
- NULL, NO_WAITBOOST);
- if (ret)
- return ret;
+ if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
+ ret = i915_sw_fence_await_dma_fence(&to->submit,
+ &from->fence, 0,
+ GFP_KERNEL);
+ if (ret < 0)
+ return ret;
+ }
} else {
ret = to->engine->semaphore.sync_to(to, from);
if (ret)
{
struct intel_engine_cs *engine = request->engine;
struct intel_ring *ring = request->ring;
+ struct drm_i915_gem_request *prev;
u32 request_start;
u32 reserved_tail;
int ret;
* hangcheck. Hence we apply the barrier to ensure that we do not
* see a more recent value in the hws than we are tracking.
*/
+
+ prev = i915_gem_active_raw(&engine->last_request,
+ &request->i915->drm.struct_mutex);
+ if (prev)
+ i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
+ &request->submitq);
+
request->emitted_jiffies = jiffies;
request->previous_seqno = engine->last_submitted_seqno;
engine->last_submitted_seqno = request->fence.seqno;
struct intel_signal_node signaling;
struct i915_sw_fence submit;
+ wait_queue_t submitq;
/** GEM sequence number associated with the previous request,
* when the HWS breadcrumb is equal to this the GPU is processing