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ntb: fix SKX NTB config space size register offsets
author
Dave Jiang
<dave.jiang@intel.com>
Tue, 13 Dec 2016 16:03:13 +0000
(09:03 -0700)
committer
Jon Mason
<jdmason@kudzu.us>
Fri, 23 Dec 2016 21:10:54 +0000
(16:10 -0500)
The offsets for the SZ registers are wrong. Updated.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Reported-by: Sandeep Mann <sandeep@purestorage.com>
Tested-by: Zachary Ross <zacharyx.ross@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
drivers/ntb/hw/intel/ntb_hw_intel.h
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diff --git
a/drivers/ntb/hw/intel/ntb_hw_intel.h
b/drivers/ntb/hw/intel/ntb_hw_intel.h
index 6e8c1824eb19e6d5a30f121272fa18a9b446b51e..f2cf8a783f1eef7c64dc49896174ee4eafc78d01 100644
(file)
--- a/
drivers/ntb/hw/intel/ntb_hw_intel.h
+++ b/
drivers/ntb/hw/intel/ntb_hw_intel.h
@@
-152,10
+152,10
@@
#define XEON_SPAD_COUNT 16
/* Intel Skylake Xeon hardware */
-#define SKX_IMBAR1SZ_OFFSET 0x00d
1
-#define SKX_IMBAR2SZ_OFFSET 0x00d
5
-#define SKX_EMBAR1SZ_OFFSET 0x00d
3
-#define SKX_EMBAR2SZ_OFFSET 0x00d
6
+#define SKX_IMBAR1SZ_OFFSET 0x00d
0
+#define SKX_IMBAR2SZ_OFFSET 0x00d
1
+#define SKX_EMBAR1SZ_OFFSET 0x00d
2
+#define SKX_EMBAR2SZ_OFFSET 0x00d
3
#define SKX_DEVCTRL_OFFSET 0x0098
#define SKX_DEVSTS_OFFSET 0x009a
#define SKX_UNCERRSTS_OFFSET 0x014c