[ARM] 4195/1: S3C2443: include/asm-arm/arch-s3c2410/regs-serial.h updates

Updates for regs-serial.h for S3C2443

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
index 46f52401d132f9e2baacd635d12bd475e4a51701..8946702a87f506f7f3c7066fa18b049a69e991c9 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -35,10 +35,12 @@
 #define S3C24XX_VA_UART0      (S3C24XX_VA_UART)
 #define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )
 #define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )
+#define S3C24XX_VA_UART3      (S3C24XX_VA_UART + 0xC000 )
 
 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
+#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
 
 #define S3C2410_URXH     (0x24)
 #define S3C2410_UTXH     (0x20)
@@ -73,6 +75,8 @@
 #define S3C2440_UCON_UCLK        (1<<10)
 #define S3C2440_UCON_PCLK2       (2<<10)
 #define S3C2440_UCON_FCLK        (3<<10)
+#define S3C2443_UCON_EPLL        (3<<10)
+
 #define S3C2440_UCON2_FCLK_EN    (1<<15)
 #define S3C2440_UCON0_DIVMASK    (15 << 12)
 #define S3C2440_UCON1_DIVMASK    (15 << 12)
@@ -93,6 +97,8 @@
 #define S3C2410_UCON_TXIRQMODE   (1<<2)
 #define S3C2410_UCON_RXIRQMODE   (1<<0)
 #define S3C2410_UCON_RXFIFO_TOI          (1<<7)
+#define S3C2443_UCON_RXERR_IRQEN  (1<<6)
+#define S3C2443_UCON_LOOPBACK    (1<<5)
 
 #define S3C2410_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL  | \
                                   S3C2410_UCON_RXILEVEL  | \
@@ -127,7 +133,7 @@
 #define        S3C2410_UMCOM_AFC         (1<<4)
 #define        S3C2410_UMCOM_RTS_LOW     (1<<0)
 
-#define S3C2412_UMCON_AFC_63   (0<<5)
+#define S3C2412_UMCON_AFC_63   (0<<5)          /* same as s3c2443 */
 #define S3C2412_UMCON_AFC_56   (1<<5)
 #define S3C2412_UMCON_AFC_48   (2<<5)
 #define S3C2412_UMCON_AFC_40   (3<<5)
@@ -143,6 +149,7 @@
 #define S3C2410_UFSTAT_RXMASK    (15<<0)
 #define S3C2410_UFSTAT_RXSHIFT   (0)
 
+/* UFSTAT S3C2443 same as S3C2440 */
 #define S3C2440_UFSTAT_TXFULL    (1<<14)
 #define S3C2440_UFSTAT_RXFULL    (1<<6)
 #define S3C2440_UFSTAT_TXSHIFT   (8)
@@ -157,6 +164,8 @@
 #define S3C2410_UERSTAT_OVERRUN          (1<<0)
 #define S3C2410_UERSTAT_FRAME    (1<<2)
 #define S3C2410_UERSTAT_BREAK    (1<<3)
+#define S3C2443_UERSTAT_PARITY   (1<<1)
+
 #define S3C2410_UERSTAT_ANY      (S3C2410_UERSTAT_OVERRUN | \
                                   S3C2410_UERSTAT_FRAME | \
                                   S3C2410_UERSTAT_BREAK)
@@ -164,6 +173,8 @@
 #define S3C2410_UMSTAT_CTS       (1<<0)
 #define S3C2410_UMSTAT_DeltaCTS          (1<<2)
 
+#define S3C2443_DIVSLOT                  (0x2C)
+
 #ifndef __ASSEMBLY__
 
 /* struct s3c24xx_uart_clksrc