drm/amdgpu:fix gfx fence allocate size
authorMonk Liu <Monk.Liu@amd.com>
Mon, 19 Jun 2017 14:19:41 +0000 (10:19 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Jul 2017 20:29:26 +0000 (16:29 -0400)
1, for sriov, we need 8dw for the gfx fence due to CP
behaviour
2, cleanup wrong logic in wptr/rptr wb alloc and free

Change-Id: Ifbfed17a4621dae57244942ffac7de1743de0294
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

index ebd077fdce1b932d1028d4e7739e2a0dd1f9928f..51d1364cf1856f0d6e3a97820f96db7ebc3c1879 100644 (file)
@@ -1192,7 +1192,9 @@ struct amdgpu_wb {
 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
+int amdgpu_wb_get_256Bit(struct amdgpu_device *adev, u32 *wb);
 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
+void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb);
 
 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 
index a9eeaad49d182804b7ddd72847947d3b6169668a..15f55865fcfbec077369035e897473838830e691 100644 (file)
@@ -602,6 +602,21 @@ int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
        }
 }
 
+int amdgpu_wb_get_256Bit(struct amdgpu_device *adev, u32 *wb)
+{
+       int i = 0;
+       unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
+                               adev->wb.num_wb, 0, 8, 63, 0);
+       if ((offset + 7) < adev->wb.num_wb) {
+               for (i = 0; i < 8; i++)
+                       __set_bit(offset + i, adev->wb.used);
+               *wb = offset;
+               return 0;
+       } else {
+               return -EINVAL;
+       }
+}
+
 /**
  * amdgpu_wb_free - Free a wb entry
  *
@@ -632,6 +647,23 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
        }
 }
 
+/**
+ * amdgpu_wb_free_256bit - Free a wb entry
+ *
+ * @adev: amdgpu_device pointer
+ * @wb: wb index
+ *
+ * Free a wb slot allocated for use by the driver (all asics)
+ */
+void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb)
+{
+       int i = 0;
+
+       if ((wb + 7) < adev->wb.num_wb)
+               for (i = 0; i < 8; i++)
+                       __clear_bit(wb + i, adev->wb.used);
+}
+
 /**
  * amdgpu_vram_location - try to find VRAM location
  * @adev: amdgpu device structure holding all necessary informations
index 75165e07b1cd8807831d4dd602a9c1a2037d8ad6..15b7149d120440eade9c53caedc799b93a5c275f 100644 (file)
@@ -212,10 +212,19 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 
        }
 
-       r = amdgpu_wb_get(adev, &ring->fence_offs);
-       if (r) {
-               dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
-               return r;
+       if (amdgpu_sriov_vf(adev) && ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+               r = amdgpu_wb_get_256Bit(adev, &ring->fence_offs);
+               if (r) {
+                       dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
+                       return r;
+               }
+
+       } else {
+               r = amdgpu_wb_get(adev, &ring->fence_offs);
+               if (r) {
+                       dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
+                       return r;
+               }
        }
 
        r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
@@ -278,17 +287,18 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
        ring->ready = false;
 
        if (ring->funcs->support_64bit_ptrs) {
-               amdgpu_wb_free_64bit(ring->adev, ring->cond_exe_offs);
-               amdgpu_wb_free_64bit(ring->adev, ring->fence_offs);
                amdgpu_wb_free_64bit(ring->adev, ring->rptr_offs);
                amdgpu_wb_free_64bit(ring->adev, ring->wptr_offs);
        } else {
-               amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
-               amdgpu_wb_free(ring->adev, ring->fence_offs);
                amdgpu_wb_free(ring->adev, ring->rptr_offs);
                amdgpu_wb_free(ring->adev, ring->wptr_offs);
        }
 
+       amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
+       if (amdgpu_sriov_vf(ring->adev) && ring->funcs->type == AMDGPU_RING_TYPE_GFX)
+               amdgpu_wb_free_256bit(ring->adev, ring->fence_offs);
+       else
+               amdgpu_wb_free(ring->adev, ring->fence_offs);
 
        amdgpu_bo_free_kernel(&ring->ring_obj,
                              &ring->gpu_addr,