ARM: OMAP: Revert "ARM: OMAP: ctrl: Fix CONTROL_DSIPHY register fields"

This reverts commit 46f8c3c7e95c0d30d95911e7975ddc4f93b3e237.

The commit above swapped the DSI1_PPID and DSI2_PPID register fields in
CONTROL_DSIPHY to be in sync with the newer public OMAP TRMs(after version V).

With this commit, contention errors were reported on DSI lanes some OMAP4 SDPs.
After probing the DSI lanes on OMAP4 SDP, it was seen that setting bits in the
DSI2_PPID field was pulling up voltage on DSI1 lanes, and DSI1_PPID field was
pulling up voltage on DSI2 lanes.

This proves that the current version of OMAP4 TRM is incorrect, swap the
position of register fields according to the older TRM versions as they were
correct.

Cc: stable@vger.kernel.org # v3.2+
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
index 1e2d3322f33eec1e644350c2aeda84718569378a..c88420de1151f9495c0ccf92aa8b718f38218b77 100644 (file)
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -941,10 +941,10 @@
 #define OMAP4_DSI2_LANEENABLE_MASK                             (0x7 << 29)
 #define OMAP4_DSI1_LANEENABLE_SHIFT                            24
 #define OMAP4_DSI1_LANEENABLE_MASK                             (0x1f << 24)
-#define OMAP4_DSI2_PIPD_SHIFT                                  19
-#define OMAP4_DSI2_PIPD_MASK                                   (0x1f << 19)
-#define OMAP4_DSI1_PIPD_SHIFT                                  14
-#define OMAP4_DSI1_PIPD_MASK                                   (0x1f << 14)
+#define OMAP4_DSI1_PIPD_SHIFT                                  19
+#define OMAP4_DSI1_PIPD_MASK                                   (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT                                  14
+#define OMAP4_DSI2_PIPD_MASK                                   (0x1f << 14)
 
 /* CONTROL_MCBSPLP */
 #define OMAP4_ALBCTRLRX_FSX_SHIFT                              31