[ERD][NEUS7920-76] [9610] arm64: dts: Add watchdog device node for FIQ Debugger
authorDonghyeok Choe <d7271.choe@samsung.com>
Fri, 14 Dec 2018 06:47:56 +0000 (15:47 +0900)
committerKim Gunho <gunho.kim@samsung.com>
Fri, 30 Aug 2019 07:58:56 +0000 (16:58 +0900)
Change-Id: Ifccfe5b7fa347a12df4169c728cbbea5fa13ecbd
Signed-off-by: Donghyeok Choe <d7271.choe@samsung.com>
arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi
arch/arm64/boot/dts/exynos/exynos9610.dtsi

index 74c6db6f71df878826d6f7d7d3bbe669cbc05a3c..65bec690bd7e8254b87a2984d04373278cf64d26 100644 (file)
@@ -21,7 +21,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
 
-               //use_multistage_wdt_irq = <497>;
+               use_multistage_wdt_irq = <265>;
                dump-info@0x0 {
                        #address-cells = <1>;
                        #size-cells = <1>;
index 7311819228ed574f86b019e9832d9906318e95ce..1317cb93ca7d7dc1a9d4dd6f214188104d0deb74 100644 (file)
                };
        };
 
-       watchdog_cl0@10050000 {
+       watchdog_cl0@10050000 { //WDT_CPUCL0
                compatible = "samsung,exynos7-wdt";
                reg = <0x0 0x10050000 0x100>;
                interrupts = <0 232 0>;
                index = <0>; /* if little cluster then index is 0*/
        };
 
+       watchdog_cl1@10060000 { //WDT_CPUCL1
+               compatible = "samsung,exynos8-wdt";
+               reg = <0x0 0x10060000 0x100>;
+               interrupts = <0 233 0>;
+               clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER1_QCH>;
+               clock-names = "rate_watchdog", "gate_watchdog";
+               timeout-sec = <30>;
+               samsung,syscon-phandle = <&pmu_system_controller>;
+               index = <1>; /* if little cluster then index is 0*/
+               use_multistage_wdt;
+       };
+
        exynos_adc: adc@11C30000 {
                compatible = "samsung,exynos-adc-v3";
                reg = <0x0 0x11C30000 0x100>;