ARM: EXYNOS5: Fix kernel dump in AFTR idle mode

The kernel crashes while resuming from AFTR idle mode. It happens
because L2 cache was not going into retention state.

This patch configures the USE_RETENTION bit of ARM_L2_OPTION register
so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of
ARM_COMMON_OPTION register for L2RSTDISABLE signal.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Tested-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 3f30aa1ae3547897410d64471cdd20eca2372b95..57344b7e98ce03b8a46dc1a3698db60ef83b6dd9 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -344,6 +344,7 @@
 #define EXYNOS5_FSYS_ARM_OPTION                                        S5P_PMUREG(0x2208)
 #define EXYNOS5_ISP_ARM_OPTION                                 S5P_PMUREG(0x2288)
 #define EXYNOS5_ARM_COMMON_OPTION                              S5P_PMUREG(0x2408)
+#define EXYNOS5_ARM_L2_OPTION                                  S5P_PMUREG(0x2608)
 #define EXYNOS5_TOP_PWR_OPTION                                 S5P_PMUREG(0x2C48)
 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION                          S5P_PMUREG(0x2CC8)
 #define EXYNOS5_JPEG_MEM_OPTION                                        S5P_PMUREG(0x2F48)

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index daebc1abc966e45a8f6b179b9276dfac3a7bf6ae..97d6885262587e763ff9b0a7a67db57e5a8a73a0 100644 (file)
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -228,6 +228,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
        { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
        { EXYNOS5_ARM_COMMON_SYS_PWR_REG,               { 0x0, 0x0, 0x2} },
        { EXYNOS5_ARM_L2_SYS_PWR_REG,                   { 0x3, 0x3, 0x3} },
+       { EXYNOS5_ARM_L2_OPTION,                        { 0x10, 0x10, 0x0 } },
        { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
        { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
        { EXYNOS5_CMU_RESET_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
@@ -353,11 +354,9 @@ static void exynos5_init_pmu(void)
 
        /*
         * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
-        * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
         */
        tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
-       tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
-               EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
+       tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
        __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
 
        /*