drm/i915/bxt: Fix off-by-one error in Broxton PLL IDs

After the commit below the Broxton PLL IDs had an off-by-one error, so
fix this up. Also add a missing brace at intel_shared_dpll_init(), it
happened to compile only due to the way the IS_BROXTON macro is defined.

v2:
- remove debugging left-over

Fixes: a3c988ea068c ("drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll code")
CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
CC: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1457978134-12362-1-git-send-email-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ed650a4f67b6b208670461536e218592b7b58a9f..4c04dab36305e0855c27998e889f1b70f940dcd3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9786,15 +9786,15 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
        switch (port) {
        case PORT_A:
                pipe_config->ddi_pll_sel = SKL_DPLL0;
-               id = DPLL_ID_SKL_DPLL1;
+               id = DPLL_ID_SKL_DPLL0;
                break;
        case PORT_B:
                pipe_config->ddi_pll_sel = SKL_DPLL1;
-               id = DPLL_ID_SKL_DPLL2;
+               id = DPLL_ID_SKL_DPLL1;
                break;
        case PORT_C:
                pipe_config->ddi_pll_sel = SKL_DPLL2;
-               id = DPLL_ID_SKL_DPLL3;
+               id = DPLL_ID_SKL_DPLL2;
                break;
        default:
                DRM_ERROR("Incorrect port type\n");

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 4b636c47e8e3c1466b9b5671cae7a106d712e478..74d5aecc0be5ad29c2ce7f6010267e1a14d72972 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1706,9 +1706,9 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
 };
 
 static const struct dpll_info bxt_plls[] = {
-       { "PORT PLL A", 0, &bxt_ddi_pll_funcs, 0 },
-       { "PORT PLL B", 1, &bxt_ddi_pll_funcs, 0 },
-       { "PORT PLL C", 2, &bxt_ddi_pll_funcs, 0 },
+       { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
+       { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
+       { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
        { NULL, -1, NULL, },
 };
 
@@ -1726,7 +1726,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
 
        if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
                dpll_mgr = &skl_pll_mgr;
-       else if IS_BROXTON(dev)
+       else if (IS_BROXTON(dev))
                dpll_mgr = &bxt_pll_mgr;
        else if (HAS_DDI(dev))
                dpll_mgr = &hsw_pll_mgr;