.name = "Asynchronous Memory Banks",
},
{
-#ifdef L2_START
.start = L2_START,
.end = L2_START + L2_LENGTH,
.psize = SIZE_1M,
.attr = SWITCH_T | I_CPLB | D_CPLB,
.i_conf = L2_MEMORY,
.d_conf = L2_MEMORY,
- .valid = 1,
-#else
- .valid = 0,
-#endif
+ .valid = (L2_LENGTH > 0),
.name = "L2 Memory",
},
{
dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
l1_data_a_length, l1_data_b_length);
-#ifdef L2_LENGTH
- l2_length = _ebss_l2 - _stext_l2;
- if (l2_length > L2_LENGTH)
- panic("L2 SRAM Overflow\n");
+ if (L2_LENGTH != 0) {
+ l2_length = _ebss_l2 - _stext_l2;
+ if (l2_length > L2_LENGTH)
+ panic("L2 SRAM Overflow\n");
- /* Copy _stext_l2 to _edata_l2 to L2 SRAM */
- dma_memcpy(_stext_l2, _l2_lma_start, l2_length);
-#endif
+ /* Copy _stext_l2 to _edata_l2 to L2 SRAM */
+ dma_memcpy(_stext_l2, _l2_lma_start, l2_length);
+ }
}
/* add_memory_region to memmap */
* we don't read something in the async space that can hang forever
*/
if ((addr >= FIXED_CODE_START && (addr + 2) <= physical_mem_end) ||
-#ifdef L2_START
+#if L2_LENGTH != 0
(addr >= L2_START && (addr + 2) <= (L2_START + L2_LENGTH)) ||
#endif
(addr >= BOOT_ROM_START && (addr + 2) <= (BOOT_ROM_START + BOOT_ROM_LENGTH)) ||
#if !L1_DATA_B_LENGTH
*(.l1.data.B)
#endif
-#ifndef L2_LENGTH
+#if !L2_LENGTH
. = ALIGN(32);
*(.data_l2.cacheline_aligned)
*(.l2.data)
__ebss_b_l1 = .;
}
-#ifdef L2_LENGTH
__l2_lma_start = .;
.text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1))
{
. = ALIGN(4);
__stext_l2 = .;
- *(.l1.text)
+ *(.l2.text)
. = ALIGN(4);
__etext_l2 = .;
. = ALIGN(4);
__sdata_l2 = .;
- *(.l1.data)
+ *(.l2.data)
__edata_l2 = .;
. = ALIGN(32);
. = ALIGN(4);
__sbss_l2 = .;
- *(.l1.bss)
+ *(.l2.bss)
. = ALIGN(4);
__ebss_l2 = .;
}
-#endif
/* Force trailing alignment of our init section so that when we
* free our init memory, we don't leave behind a partial page.
static struct sram_piece free_l1_inst_sram_head, used_l1_inst_sram_head;
#endif
-#ifdef L2_LENGTH
+#if L2_LENGTH != 0
static struct sram_piece free_l2_sram_head, used_l2_sram_head;
#endif
static void __init l2_sram_init(void)
{
-#ifdef L2_LENGTH
+#if L2_LENGTH != 0
free_l2_sram_head.next =
kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
if (!free_l2_sram_head.next) {
&& addr < (void *)(L1_DATA_B_START + L1_DATA_B_LENGTH))
return l1_data_B_sram_free(addr);
#endif
-#ifdef L2_LENGTH
+#if L2_LENGTH != 0
else if (addr >= (void *)L2_START
&& addr < (void *)(L2_START + L2_LENGTH))
return l2_sram_free(addr);
void *l2_sram_alloc(size_t size)
{
-#ifdef L2_LENGTH
+#if L2_LENGTH != 0
unsigned flags;
void *addr;
int l2_sram_free(const void *addr)
{
-#ifdef L2_LENGTH
+#if L2_LENGTH != 0
unsigned flags;
int ret;
&free_l1_inst_sram_head, &used_l1_inst_sram_head))
goto not_done;
#endif
-#ifdef L2_LENGTH
+#if L2_LENGTH != 0
if (_sram_proc_read(buf, &len, count, "L2",
&free_l2_sram_head, &used_l2_sram_head))
goto not_done;
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE */
+/* Level 2 Memory - none */
+
+#define L2_START 0
+#define L2_LENGTH 0
+
/* Scratch Pad Memory */
#define L1_SCRATCH_START 0xFFB00000
#endif
+/* Level 2 Memory - none */
+
+#define L2_START 0
+#define L2_LENGTH 0
+
/* Scratch Pad Memory */
#define L1_SCRATCH_START 0xFFB00000
#endif
+/* Level 2 Memory - none */
+
+#define L2_START 0
+#define L2_LENGTH 0
+
/* Scratch Pad Memory */
#define L1_SCRATCH_START 0xFFB00000