clk: tegra: Special-case mipi-cal parent on Tegra114

Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its
source. On Tegra114 this clock's parent was clk_m, so it is the one-off
chip.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index b4e226a2f42c1684b00a8456b585f37095e89c6d..463c114358e657f98b05dfad92ff5266a681352b 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -803,7 +803,7 @@ static struct tegra_periph_init_data gate_clks[] = {
        GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
        GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
        GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
-       GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0),
+       GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
        GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
        GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
        GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index df47ec3169c3451b67147d60cba3da83ec5e565b..b78054fac0a8771c7a892b7478b93722a9c1c65a 100644 (file)
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -743,7 +743,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
        [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
        [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
        [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
-       [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
        [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
        [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
        [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
@@ -1237,6 +1236,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
                                    &emc_lock);
        clks[TEGRA114_CLK_MC] = clk;
 
+       clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
+                                            CLK_SET_RATE_PARENT, 56,
+                                            periph_clk_enb_refcnt);
+       clks[TEGRA114_CLK_MIPI_CAL] = clk;
+
        for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
                data = &tegra_periph_clk_list[i];
                clk = tegra_clk_register_periph(data->name,