ARM: dts: qcom: Add idle state device nodes for 8064

Add ARM common idle state device bindings for cpuidle support for APQ
8064.

Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 58e1d79185ce8a4f098d8629f1ccc639c0f7ac5b..6c1511263a55deacd582b96bd4c57edad59300a8 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -23,6 +23,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc0>;
                        qcom,saw = <&saw0>;
+                       cpu-idle-states = <&CPU_SPC>;
                };
 
                cpu@1 {
@@ -33,6 +34,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc1>;
                        qcom,saw = <&saw1>;
+                       cpu-idle-states = <&CPU_SPC>;
                };
 
                cpu@2 {
@@ -43,6 +45,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc2>;
                        qcom,saw = <&saw2>;
+                       cpu-idle-states = <&CPU_SPC>;
                };
 
                cpu@3 {
@@ -53,12 +56,23 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc3>;
                        qcom,saw = <&saw3>;
+                       cpu-idle-states = <&CPU_SPC>;
                };
 
                L2: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
                };
+
+               idle-states {
+                       CPU_SPC: spc {
+                               compatible = "qcom,idle-state-spc",
+                                               "arm,idle-state";
+                               entry-latency-us = <400>;
+                               exit-latency-us = <900>;
+                               min-residency-us = <3000>;
+                       };
+               };
        };
 
        cpu-pmu {