PD #94239: disable clock in pm_rt and enlarge pmu_sw_delay

Change-Id: Ida9b17070fd06d98bb9854193b77887c9c107141

diff --git a/mali/common/mali_pmu.c b/mali/common/mali_pmu.c
index 316519e0ddf6a4cec33187f37455cdf33c94933a..fc0d76af8da4e88dec09402c6d9ccd6ef1791ba0 100755 (executable)
--- a/mali/common/mali_pmu.c
+++ b/mali/common/mali_pmu.c
@@ -132,6 +132,11 @@ static _mali_osk_errcode_t mali_pmu_wait_for_command_finish(struct mali_pmu_core
 static _mali_osk_errcode_t mali_pmu_power_up_internal(struct mali_pmu_core *pmu, const u32 mask)
 {
        u32 stat;
+       u32 active_mask;
+       u32 mask_ck;
+       u32 swt_dly;
+       u32 xxd = 1;
+
        _mali_osk_errcode_t err;
 #if !defined(CONFIG_MALI_PMU_PARALLEL_POWER_UP)
        u32 current_domain;
@@ -153,8 +158,17 @@ static _mali_osk_errcode_t mali_pmu_power_up_internal(struct mali_pmu_core *pmu,
                return err;
        }
 #else
+       active_mask = mask & stat;
+       mask_ck = active_mask;
        for (current_domain = 1; current_domain <= pmu->registered_cores_mask; current_domain <<= 1) {
-               if (current_domain & mask & stat) {
+               if (current_domain & active_mask) {
+                       if (mask_ck == 1) {
+                               swt_dly = pmu->switch_delay;
+                               xxd = 0;
+                       }
+                       else
+                               swt_dly = 0xfff;
+                       mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, swt_dly);
                        mali_hw_core_register_write(&pmu->hw_core, PMU_REG_ADDR_MGMT_POWER_UP, current_domain);
 
                        err = mali_pmu_wait_for_command_finish(pmu);
@@ -162,7 +176,16 @@ static _mali_osk_errcode_t mali_pmu_power_up_internal(struct mali_pmu_core *pmu,
                                return err;
                        }
                }
+               mask_ck = mask_ck >> 1;
        }
+       if (xxd != 0) {
+               printk("@@@@ warn\n");
+               printk("mask_ck:%d,active_mask:%d\n", mask_ck, active_mask);
+               //panic(0);
+        }
+        if (swt_dly != pmu->switch_delay)
+               mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
+
 #endif
 
 #if defined(DEBUG)

diff --git a/mali/platform/meson_m450/platform_m8b.c b/mali/platform/meson_m450/platform_m8b.c
index b34d81c3b6e13a2310cdfa19997067e3f02264d2..261bdc3f03f1c743197e64d2523a4f0e1b98bcb9 100755 (executable)
--- a/mali/platform/meson_m450/platform_m8b.c
+++ b/mali/platform/meson_m450/platform_m8b.c
@@ -43,7 +43,7 @@
 #define FCLK_DEV5 (7 << 9)             /*      510   Mhz  */
 #define FCLK_DEV7 (4 << 9)             /*      364.3 Mhz  */
 
-u32 mali_dvfs_clk[] = {
+static u32 mali_dvfs_clk[] = {
        FCLK_DEV5 | 1,     /* 255 Mhz */
        FCLK_DEV7 | 0,     /* 364 Mhz */
        FCLK_DEV3 | 1,     /* 425 Mhz */
@@ -51,7 +51,7 @@ u32 mali_dvfs_clk[] = {
        FCLK_DEV4 | 0,     /* 637.5 Mhz */
 };
 
-u32 mali_dvfs_clk_sample[] = {
+static u32 mali_dvfs_clk_sample[] = {
        255,     /* 182.1 Mhz */
        364,     /* 318.7 Mhz */
        425,     /* 425 Mhz */
@@ -91,9 +91,9 @@ static mali_plat_info_t mali_plat_data = {
 
        .scale_info = {
                CFG_MIN_PP, /* minpp */
-               CFG_PP, /* maxpp, should be same as cfg_pp */ 
-               CFG_MIN_CLOCK, /* minclk */ 
-               CFG_CLOCK, /* maxclk should be same as cfg_clock */ 
+               CFG_PP, /* maxpp, should be same as cfg_pp */
+               CFG_MIN_CLOCK, /* minclk */
+               CFG_CLOCK, /* maxclk should be same as cfg_clock */
        },
 
        .limit_on = 1,

diff --git a/mali/platform/meson_m450/platform_m8m2.c b/mali/platform/meson_m450/platform_m8m2.c
index 5346b01469aeca753a63c4dac94b62ca6c57c048..7504d6bdf758aea090a45c8b98044eee5f6cae9a 100755 (executable)
--- a/mali/platform/meson_m450/platform_m8m2.c
+++ b/mali/platform/meson_m450/platform_m8m2.c
@@ -284,6 +284,7 @@ static int mali_cri_light_suspend(size_t param)
        struct mali_pmu_core *pmu;
 
        ret = 0;
+       mali_pm_statue = 0;
        device = (struct device *)param;
        pmu = mali_pmu_get_global_pmu_core();
 
@@ -316,6 +317,7 @@ static int mali_cri_light_resume(size_t param)
                /* Need to notify Mali driver about this event */
                ret = device->driver->pm->runtime_resume(device);
        }
+       mali_pm_statue = 1;
        return ret;
 }
 
@@ -374,14 +376,14 @@ int mali_light_suspend(struct device *device)
 
        /* clock scaling. Kasin..*/
        ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
-
+       disable_clock();
        return ret;
 }
 
 int mali_light_resume(struct device *device)
 {
        int ret = 0;
-
+       enable_clock();
        ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
 #ifdef CONFIG_MALI400_PROFILING
        _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |

diff --git a/mali/platform/meson_m450/scaling.c b/mali/platform/meson_m450/scaling.c
index cf9edd5f74b21749f88e98f69189b8d55392a747..4d64df4b37748a65ae472c7b4fa430735957f314 100755 (executable)
--- a/mali/platform/meson_m450/scaling.c
+++ b/mali/platform/meson_m450/scaling.c
@@ -346,18 +346,25 @@ void set_mali_schel_mode(u32 mode)
        if (mode >= MALI_SCALING_MODE_MAX)
                return;
        scaling_mode = mode;
-       if (scaling_mode != MALI_PP_FS_SCALING) {
-               pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
+
+       /* set default performance range. */
+       pmali_plat->scale_info.minclk = pmali_plat->cfg_min_clock;
+       pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+       pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
+       pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
+
+       /* set current status and tune max freq */
+       if (scaling_mode == MALI_PP_FS_SCALING) {
+               pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
+               enable_pp_cores(pmali_plat->sc_mpp);
+       } else if (scaling_mode == MALI_SCALING_DISABLE) {
                pmali_plat->scale_info.maxclk = pmali_plat->cfg_clock;
-               pmali_plat->scale_info.minpp = pmali_plat->cfg_min_pp;
-               pmali_plat->scale_info.maxpp = pmali_plat->cfg_pp;
+               enable_max_num_cores();
+       } else if (scaling_mode == MALI_TURBO_MODE) {
+               pmali_plat->scale_info.maxclk = pmali_plat->turbo_clock;
+               enable_max_num_cores();
        }
-       if (scaling_mode == MALI_TURBO_MODE) {
-               currentStep = pmali_plat->turbo_clock;
-               pmali_plat->scale_info.maxclk = currentStep;
-       } else
-               currentStep = pmali_plat->scale_info.maxclk;
-       enable_max_num_cores();
+       currentStep = pmali_plat->scale_info.maxclk;
        schedule_work(&wq_work);
 }