ARM: dts: mt8127: enable basic SMP bringup for mt8127

Add arch timer node to enable arch-timer support. MT8127 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.

This also set cpu enable-method to enable SMP.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index ca3402e8240be1478568f23622c3bed965e06cfa..52086c8018e203648db36fd6b715d866935f3d34 100644 (file)
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -23,6 +23,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               enable-method = "mediatek,mt81xx-tz-smp";
 
                cpu@0 {
                        device_type = "cpu";
@@ -47,6 +48,17 @@
 
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               trustzone-bootinfo@80002000 {
+                       compatible = "mediatek,trustzone-bootinfo";
+                       reg = <0 0x80002000 0 0x1000>;
+               };
+       };
+
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -72,6 +84,21 @@
                 };
        };
 
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_LOW)>;
+               clock-frequency = <13000000>;
+               arm,cpu-registers-not-fw-configured;
+       };
+
        soc {
                #address-cells = <2>;
                #size-cells = <2>;