clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks

Add clock hierarchy for Security SubSystem clock and watchdog.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index 2ddf954e0099f98340e6a17a243cbe3725f05468..54ec486a5e45c2c1fdb2e203edd67e7c0b761093 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -31,6 +31,7 @@
 #define SRC_CPU                        0x200
 #define DIV_CPU0               0x500
 #define SRC_CPERI1             0x4204
+#define GATE_IP_G2D            0x8800
 #define DIV_TOP0               0x10510
 #define DIV_TOP1               0x10514
 #define DIV_FSYS0              0x10548
@@ -154,11 +155,14 @@ static const struct samsung_div_clock exynos5410_div_clks[] __initconst = {
        DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
 
        DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+       DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
        DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
 };
 
 static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
+       GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
        GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+       GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
        GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
        GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),