drm/i915: Invariably invalidate before ctx switch

We have been setting the bit which was originally BIOS dependent since:
commit f05bb0c7b624252a5e768287e340e8e45df96e42
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Sun Jan 20 16:33:32 2013 +0000

    drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits

Therefore, we do not need to try to figure it out dynamically and we can
just always invalidate the TLBs.

It's a partial revert of:
commit 12b0286f49947a6cdc9285032d918466a8c3f5f9
Author: Ben Widawsky <ben@bwidawsk.net>
Date:   Mon Jun 4 14:42:50 2012 -0700

    drm/i915: possibly invalidate TLB before context switch

The original commit attempted to only invalidate when necessary
(very much a relic from the old days). Now, we can just always invalidate.

I guess the old TODO still exists. Since we seem to have abandoned ILK
contexts however, there isn't much point in even remembering.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index edbad2787d65fbeb22e4e1e1fa72f976a499c8ed..8827892a099d51ec342ecd405456acde9ea07e08 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -596,7 +596,7 @@ mi_set_context(struct intel_ring_buffer *ring,
         * explicitly, so we rely on the value at ring init, stored in
         * itlb_before_ctx_switch.
         */
-       if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
+       if (IS_GEN6(ring->dev)) {
                ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
                if (ret)
                        return ret;

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 785f246d28a8e812ae285cb3f242e6d4d0cec6c0..fb3eeb0705c95b4f0a2c6dc40080c48cb2263596 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -612,13 +612,6 @@ static int init_render_ring(struct intel_ring_buffer *ring)
                 */
                I915_WRITE(CACHE_MODE_0,
                           _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
-
-               /* This is not explicitly set for GEN6, so read the register.
-                * see intel_ring_mi_set_context() for why we care.
-                * TODO: consider explicitly setting the bit for GEN5
-                */
-               ring->itlb_before_ctx_switch =
-                       !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_EXPLICIT);
        }
 
        if (INTEL_INFO(dev)->gen >= 6)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 270a6a9734387b6079e9348e17773214a293ad0a..9e913633eb6cd29fc80f8885e0aa0258f62a4541 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -152,10 +152,6 @@ struct  intel_ring_buffer {
 
        wait_queue_head_t irq_queue;
 
-       /**
-        * Do an explicit TLB flush before MI_SET_CONTEXT
-        */
-       bool itlb_before_ctx_switch;
        struct i915_hw_context *default_context;
        struct i915_hw_context *last_context;