drm/i915/bxt: add missing DDI PLL registers to the state checking

Although we have a fixed setting for the PLL9 and EBB4 registers, it
still makes sense to check them together with the rest of PLL registers.

While at it also remove a redundant comment about 10 bit clock enabling.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 64041e788a1c75d41716dcf9f6feef49088a9f73..1dbd95710bf4fc0bc321699c1b353ae944d037ac 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -372,7 +372,8 @@ struct intel_dpll_hw_state {
        uint32_t cfgcr1, cfgcr2;
 
        /* bxt */
-       uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
+       uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
+                pcsdw12;
 };
 
 struct intel_shared_dpll_config {

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bdef9f7b629e06e00644631d9e699ae7d04be670..4d8ef2de4374c468ea250bdc88c252cbdf9a0843 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1208,7 +1208,8 @@ enum skl_disp_power_wells {
 /* PORT_PLL_8_A */
 #define   PORT_PLL_TARGET_CNT_MASK     0x3FF
 /* PORT_PLL_9_A */
-#define  PORT_PLL_LOCK_THRESHOLD_MASK  0xe
+#define  PORT_PLL_LOCK_THRESHOLD_SHIFT 1
+#define  PORT_PLL_LOCK_THRESHOLD_MASK  (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
 /* PORT_PLL_10_A */
 #define  PORT_PLL_DCO_AMP_OVR_EN_H     (1<<27)
 #define  PORT_PLL_DCO_AMP_MASK         0x3c00

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b29d103bd706a839f2585fcd766650d61ad4988f..cf2896da8ad80681a503ca8aea203d6f52f9b191 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1722,11 +1722,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 
        crtc_state->dpll_hw_state.pll8 = targ_cnt;
 
+       crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
+
        if (dcoampovr_en_h)
                crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
 
        crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
 
+       crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
+
        crtc_state->dpll_hw_state.pcsdw12 =
                LANESTAGGER_STRAP_OVRD | lanestagger;
 
@@ -2767,7 +2771,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
 
        temp = I915_READ(BXT_PORT_PLL(port, 9));
        temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
-       temp |= (5 << 1);
+       temp |= pll->config.hw_state.pll9;
        I915_WRITE(BXT_PORT_PLL(port, 9), temp);
 
        temp = I915_READ(BXT_PORT_PLL(port, 10));
@@ -2780,8 +2784,8 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
        temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
        temp |= PORT_PLL_RECALIBRATE;
        I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
-       /* Enable 10 bit clock */
-       temp |= PORT_PLL_10BIT_CLK_ENABLE;
+       temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
+       temp |= pll->config.hw_state.ebb4;
        I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
 
        /* Enable PLL */
@@ -2832,12 +2836,18 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
                return false;
 
        hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
+       hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
+       hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
+
        hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
        hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
        hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
        hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
        hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
        hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
+       hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
+       hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
+
        hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
        /*
         * While we write to the group register to program all lanes at once we

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b7d42e6aac1090102454c93b44ced28e87695a0c..6be8768459318ab86c4a54541248583791589dbe 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12012,17 +12012,19 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
        DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
 
        if (IS_BROXTON(dev)) {
-               DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
+               DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
                              "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
-                             "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
+                             "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pcsdw12: 0x%x\n",
                              pipe_config->ddi_pll_sel,
                              pipe_config->dpll_hw_state.ebb0,
+                             pipe_config->dpll_hw_state.ebb4,
                              pipe_config->dpll_hw_state.pll0,
                              pipe_config->dpll_hw_state.pll1,
                              pipe_config->dpll_hw_state.pll2,
                              pipe_config->dpll_hw_state.pll3,
                              pipe_config->dpll_hw_state.pll6,
                              pipe_config->dpll_hw_state.pll8,
+                             pipe_config->dpll_hw_state.pll9,
                              pipe_config->dpll_hw_state.pcsdw12);
        } else if (IS_SKYLAKE(dev)) {
                DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "