GPIO95_AC97_nRESET,
};
-void pxa27x_assert_ac97reset(int reset_gpio, int on)
+void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
{
+ /*
+ * This helper function is used to work around a bug in the pxa27x's
+ * ac97 controller during a warm reset. The configuration of the
+ * reset_gpio is changed as follows:
+ * to_gpio == true: configured to generic output gpio and driven high
+ * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
+ */
+
if (reset_gpio == 113)
- pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
- &ac97_reset_config[1], 1);
+ pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
+ &ac97_reset_config[1], 1);
if (reset_gpio == 95)
- pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
- &ac97_reset_config[3], 1);
+ pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
+ &ac97_reset_config[3], 1);
}
-EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
+EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
/* Crystal clock: 13MHz */
#define BASE_CLK 13000000
static struct clk *ac97conf_clk;
static int reset_gpio;
-extern void pxa27x_assert_ac97reset(int reset_gpio, int on);
+extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
/*
* Beware PXA27x bugs:
gsr_bits = 0;
/* warm reset broken on Bulverde, so manually keep AC97 reset high */
- pxa27x_assert_ac97reset(reset_gpio, 1);
+ pxa27x_configure_ac97reset(reset_gpio, true);
udelay(10);
GCR |= GCR_WARM_RST;
- pxa27x_assert_ac97reset(reset_gpio, 0);
+ pxa27x_configure_ac97reset(reset_gpio, false);
udelay(500);
}
__func__, ret);
goto err_conf;
}
- pxa27x_assert_ac97reset(reset_gpio, 0);
+ pxa27x_configure_ac97reset(reset_gpio, false);
ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
if (IS_ERR(ac97conf_clk)) {