mmc: tmio: add flag to reduce delay after changing clock status

The docs for RCar Gen2 & 3 I have access to, mention delays of 5ms after
stop and 1ms after start. Make it possible to apply these values.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c
index a10fde40b6c3ddbed98e05a693336ea6b1bb1c65..ffff687e98b1e3aabb40ed62e66001a2682878ed 100644 (file)
--- a/drivers/mmc/host/tmio_mmc_pio.c
+++ b/drivers/mmc/host/tmio_mmc_pio.c
@@ -172,7 +172,8 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
                host->set_clk_div(host->pdev, (clk>>22) & 1);
 
        sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
-       msleep(10);
+       if (!(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG))
+               msleep(10);
 }
 
 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
@@ -185,14 +186,14 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
 
        sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
                sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
-       msleep(10);
+       msleep(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG ? 5 : 10);
 }
 
 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
 {
        sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
                sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
-       msleep(10);
+       msleep(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG ? 1 : 10);
 
        /* implicit BUG_ON(!res) */
        if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {

diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index 24b86d538e8852eef94cc020a7f92230dcfacedd..05d58ee5e6a78fb4d8366b2391d84a2f4838aa82 100644 (file)
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -65,6 +65,10 @@
  * Some controllers can support SDIO IRQ signalling.
  */
 #define TMIO_MMC_SDIO_IRQ              (1 << 2)
+
+/* Some controllers don't need to wait 10ms for clock changes */
+#define TMIO_MMC_FAST_CLK_CHG          (1 << 3)
+
 /*
  * Some controllers require waiting for the SD bus to become
  * idle before writing to some registers.