mtd: fsl-quadspi: fix macro collision problems with READ/WRITE

Change the READ/WRITE to FSL_READ/FSL_WRITE to resolve any possible
namespace collisions with READ/WRITE macros (e.g., from <linux/fs.h>).

Problems have been seen, for example, on mips:

>> drivers/mtd/spi-nor/fsl-quadspi.c:186:5: error: 'LUT_0' undeclared (first use in this function)
      ((LUT_##ins) << INSTR0_SHIFT))
        ^
>> drivers/mtd/spi-nor/fsl-quadspi.c:188:30: note: in expansion of macro 'LUT0'

On SPARC:

drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_init_lut':
drivers/mtd/spi-nor/fsl-quadspi.c:369:1: error: 'LUT_0' undeclared (first use in this function)
drivers/mtd/spi-nor/fsl-quadspi.c:418:1: error: pasting "LUT_" and "(" does not give a valid preprocessing token
drivers/mtd/spi-nor/fsl-quadspi.c:418:2: error: implicit declaration of function 'LUT_'

And surely on others.

Fixes: d26a22d06708 ("mtd: fsl-quadspi: allow building for other ARCHes with COMPILE_TEST")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Han Xu <b45815@freescale.com>
[Brian: rewrote commit description]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index dc383895792c68abf38ac9be9f84485dfcfee52a..7b10ed413983aecbc2b51a30b6bcdd1d98a1fa85 100644 (file)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -155,15 +155,15 @@
 #define LUT_MODE               4
 #define LUT_MODE2              5
 #define LUT_MODE4              6
-#define LUT_READ               7
-#define LUT_WRITE              8
+#define LUT_FSL_READ           7
+#define LUT_FSL_WRITE          8
 #define LUT_JMP_ON_CS          9
 #define LUT_ADDR_DDR           10
 #define LUT_MODE_DDR           11
 #define LUT_MODE2_DDR          12
 #define LUT_MODE4_DDR          13
-#define LUT_READ_DDR           14
-#define LUT_WRITE_DDR          15
+#define LUT_FSL_READ_DDR               14
+#define LUT_FSL_WRITE_DDR              15
 #define LUT_DATA_LEARN         16
 
 /*
@@ -366,7 +366,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
        writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
                        base + QUADSPI_LUT(lut_base));
-       writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
+       writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
                        base + QUADSPI_LUT(lut_base + 1));
 
        /* Write enable */
@@ -387,11 +387,11 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
        writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
                        base + QUADSPI_LUT(lut_base));
-       writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+       writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
 
        /* Read Status */
        lut_base = SEQID_RDSR * 4;
-       writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
+       writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
                        base + QUADSPI_LUT(lut_base));
 
        /* Erase a sector */
@@ -410,17 +410,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
        /* READ ID */
        lut_base = SEQID_RDID * 4;
-       writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
+       writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8),
                        base + QUADSPI_LUT(lut_base));
 
        /* Write Register */
        lut_base = SEQID_WRSR * 4;
-       writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
+       writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2),
                        base + QUADSPI_LUT(lut_base));
 
        /* Read Configuration Register */
        lut_base = SEQID_RDCR * 4;
-       writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
+       writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1),
                        base + QUADSPI_LUT(lut_base));
 
        /* Write disable */