drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 95303e2d5f92707f31ec2a86bef4b6e7497e9c8f..dadb6abd4d3e4a622809326f2bc4c7d4b662a325 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -724,19 +724,6 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
 }
 #endif
 
-static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
-{
-       u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
-
-       if (enable)
-               tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
-                       GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
-       else
-               tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
-                        GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
-
-       WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
-}
 
 static int uvd_v5_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
@@ -745,8 +732,6 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
        bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
        static int curstate = -1;
 
-       uvd_v5_0_set_bypass_mode(adev, enable);
-
        if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
                return 0;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index a339b5ccb2965dcac9f0885888079a477cee747f..00fad6951d82420a1c188679b534eac709236b00 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -151,6 +151,8 @@ static int uvd_v6_0_hw_init(void *handle)
        uint32_t tmp;
        int r;
 
+       amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
+
        r = uvd_v6_0_start(adev);
        if (r)
                goto done;
@@ -935,28 +937,12 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
 }
 #endif
 
-static void uvd_v6_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
-{
-       u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
-
-       if (enable)
-               tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
-                       GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
-       else
-               tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
-                        GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
-
-       WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
-}
-
 static int uvd_v6_0_set_clockgating_state(void *handle,
                                          enum amd_clockgating_state state)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 
-       uvd_v6_0_set_bypass_mode(adev, enable);
-
        if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
                return 0;