drm/amd/powerplay: add all blocks clockgating support through SMU/powerplay

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 9d2290044708d7f2119c702ddc45d15c77b6b808..9c742e0a9d358c20862e3d0f3a369f7a6040fe8a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -180,6 +180,87 @@ static void pp_print_status(void *handle)
 static int pp_set_clockgating_state(void *handle,
                                    enum amd_clockgating_state state)
 {
+       struct pp_hwmgr  *hwmgr;
+       uint32_t msg_id, pp_state;
+
+       if (handle == NULL)
+               return -EINVAL;
+
+       hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+       if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
+                       hwmgr->hwmgr_func->update_clock_gatings == NULL)
+                       return -EINVAL;
+
+       if (state == AMD_CG_STATE_UNGATE)
+               pp_state = 0;
+       else
+               pp_state = PP_STATE_CG | PP_STATE_LS;
+
+       /* Enable/disable GFX blocks clock gating through SMU */
+       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                       PP_BLOCK_GFX_CG,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                       PP_BLOCK_GFX_3D,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                       PP_BLOCK_GFX_RLC,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                       PP_BLOCK_GFX_CP,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                       PP_BLOCK_GFX_MG,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+
+       /* Enable/disable System blocks clock gating through SMU */
+       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                       PP_BLOCK_SYS_BIF,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                       PP_BLOCK_SYS_BIF,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                       PP_BLOCK_SYS_MC,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                       PP_BLOCK_SYS_ROM,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                       PP_BLOCK_SYS_DRM,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                       PP_BLOCK_SYS_HDP,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                       PP_BLOCK_SYS_SDMA,
+                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_state);
+       hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+
        return 0;
 }
 

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 7255f7ddf93a288feb6c6f4166c5f3d3a7187cae..e5f2ee749fa6758347139b3128f47b2b0fa1139c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -289,6 +289,9 @@ struct pp_states_info {
 
 #define PP_BLOCK_GFX_CG         0x01
 #define PP_BLOCK_GFX_MG         0x02
+#define PP_BLOCK_GFX_3D         0x04
+#define PP_BLOCK_GFX_RLC        0x08
+#define PP_BLOCK_GFX_CP         0x10
 #define PP_BLOCK_SYS_BIF        0x01
 #define PP_BLOCK_SYS_MC         0x02
 #define PP_BLOCK_SYS_ROM        0x04