#define use_vga_switcheroo(chip) 0
#endif
+#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
+ ((pci)->device == 0x0c0c) || \
+ ((pci)->device == 0x0d0c) || \
+ ((pci)->device == 0x160c))
+
static char *driver_short_names[] = {
[AZX_DRIVER_ICH] = "HDA Intel",
[AZX_DRIVER_PCH] = "HDA Intel PCH",
* display codec needs the power and it can be released after probe.
*/
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
- /* Baytral/Braswell controllers don't need this power */
- if (pci->device != 0x0f04 && pci->device != 0x2284)
+ /* HSW/BDW controllers need this power */
+ if (CONTROLLER_IN_GPU(pci))
hda->need_i915_power = 1;
err = snd_hdac_i915_init(bus);
* can cover the codec power request, and so need not set this flag.
* For previous platforms, there is no such power well feature.
*/
- if (is_valleyview_plus(codec))
+ if (is_valleyview_plus(codec) || is_skylake(codec))
codec->core.link_power_control = 1;
if (is_haswell_plus(codec) || is_valleyview_plus(codec))