drm/radeon: Restrict offset for legacy display engine.
authorMichel Dänzer <michel.daenzer@amd.com>
Wed, 14 Mar 2012 16:12:42 +0000 (17:12 +0100)
committerDave Airlie <airlied@redhat.com>
Tue, 20 Mar 2012 08:47:46 +0000 (08:47 +0000)
The hardware only takes 27 bits for the offset, so larger offsets are
truncated, and the display shows random bits other than the intended ones.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_fb.c
drivers/gpu/drm/radeon/radeon_legacy_crtc.c

index b25bb2a55814456ba9c47ced12998ca1935d89f5..1ebcef25b9155de3d4bf266d1d62a84b835faef3 100644 (file)
@@ -402,7 +402,9 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
                DRM_ERROR("failed to reserve new rbo buffer before flip\n");
                goto pflip_cleanup;
        }
-       r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
+       /* Only 27 bit offset for legacy CRTC */
+       r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
+                                    ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
        if (unlikely(r != 0)) {
                radeon_bo_unreserve(rbo);
                r = -EINVAL;
index 60b97ab1d19e083f1b25299b7eb76df608dc7d91..5906914a78bc3ad38407b19453b8f3b321acbd98 100644 (file)
@@ -164,7 +164,10 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
        ret = radeon_bo_reserve(rbo, false);
        if (unlikely(ret != 0))
                goto out_unref;
-       ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
+       /* Only 27 bit offset for legacy CRTC */
+       ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
+                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
+                                      NULL);
        if (ret) {
                radeon_bo_unreserve(rbo);
                goto out_unref;
index 25a19c483075650725d8bdb7a6af68ff993f1a5d..210317c7045ef11daf4565f66d471fa04043dbbf 100644 (file)
@@ -419,7 +419,9 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
        r = radeon_bo_reserve(rbo, false);
        if (unlikely(r != 0))
                return r;
-       r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
+       /* Only 27 bit offset for legacy CRTC */
+       r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
+                                    &base);
        if (unlikely(r != 0)) {
                radeon_bo_unreserve(rbo);
                return -EINVAL;