V4L/DVB (13583): DiB8090: Add the DiB0090 tuner driver and STK8096GP-board
authorOlivier Grenie <Olivier.Grenie@dibcom.fr>
Fri, 4 Dec 2009 16:27:57 +0000 (13:27 -0300)
committerMauro Carvalho Chehab <mchehab@redhat.com>
Wed, 16 Dec 2009 02:18:16 +0000 (00:18 -0200)
This patchs adds support for the DiBcom DiB0090 RF tuner and for
DiBcom's reference design STK8096GP. Small extracts of the DiB0070 and
the DiB8000-driver into a common codebase.

Signed-off-by: Patrick Boettcher <pboettcher@kernellabs.com>
Signed-off-by: Olivier Grenie <Olivier.Grenie@dibcom.fr>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
12 files changed:
drivers/media/dvb/dvb-usb/dib0700_devices.c
drivers/media/dvb/dvb-usb/dvb-usb-ids.h
drivers/media/dvb/frontends/Kconfig
drivers/media/dvb/frontends/Makefile
drivers/media/dvb/frontends/dib0070.c
drivers/media/dvb/frontends/dib0070.h
drivers/media/dvb/frontends/dib0090.c [new file with mode: 0644]
drivers/media/dvb/frontends/dib0090.h [new file with mode: 0644]
drivers/media/dvb/frontends/dib8000.c
drivers/media/dvb/frontends/dib8000.h
drivers/media/dvb/frontends/dibx000_common.c
drivers/media/dvb/frontends/dibx000_common.h

index 923fa157aa51096a72bf6651b77d4b5740b0dcd5..80a126354477cd2b499bcb4d280036d9c573ba6c 100644 (file)
@@ -18,6 +18,7 @@
 #include "xc5000.h"
 #include "s5h1411.h"
 #include "dib0070.h"
+#include "dib0090.h"
 #include "lgdt3305.h"
 #include "mxl5007t.h"
 
@@ -605,17 +606,17 @@ static int dib0700_rc_query_v1_20(struct dvb_usb_device *d, u32 *event,
                }
                break;
        default:
-               if (actlen != sizeof(buf)) {
-                       /* We didn't get back the 6 byte message we expected */
-                       err("Unexpected RC response size [%d]", actlen);
-                       return -1;
-               }
+       if (actlen != sizeof(buf)) {
+               /* We didn't get back the 6 byte message we expected */
+               err("Unexpected RC response size [%d]", actlen);
+               return -1;
+       }
 
-               poll_reply.report_id  = buf[0];
-               poll_reply.data_state = buf[1];
+       poll_reply.report_id  = buf[0];
+       poll_reply.data_state = buf[1];
                poll_reply.system     = (buf[2] << 8) | buf[3];
-               poll_reply.data       = buf[4];
-               poll_reply.not_data   = buf[5];
+       poll_reply.data       = buf[4];
+       poll_reply.not_data   = buf[5];
 
                break;
        }
@@ -632,7 +633,7 @@ static int dib0700_rc_query_v1_20(struct dvb_usb_device *d, u32 *event,
        /* Find the key in the map */
        for (i = 0; i < d->props.rc_key_map_size; i++) {
                if (rc5_custom(&keymap[i]) == (poll_reply.system & 0xff) &&
-                   rc5_data(&keymap[i]) == poll_reply.data) {
+                       rc5_data(&keymap[i]) == poll_reply.data) {
                        *event = keymap[i].event;
                        found = 1;
                        break;
@@ -641,8 +642,8 @@ static int dib0700_rc_query_v1_20(struct dvb_usb_device *d, u32 *event,
 
        if (found == 0) {
                err("Unknown remote controller key: %04x %02x %02x",
-                   poll_reply.system,
-                   poll_reply.data, poll_reply.not_data);
+                       poll_reply.system,
+                       poll_reply.data, poll_reply.not_data);
                d->last_event = 0;
                return 0;
        }
@@ -1476,12 +1477,12 @@ static struct dib8000_config dib807x_dib8000_config[2] = {
        }
 };
 
-static int dib807x_tuner_reset(struct dvb_frontend *fe, int onoff)
+static int dib80xx_tuner_reset(struct dvb_frontend *fe, int onoff)
 {
        return dib8000_set_gpio(fe, 5, 0, !onoff);
 }
 
-static int dib807x_tuner_sleep(struct dvb_frontend *fe, int onoff)
+static int dib80xx_tuner_sleep(struct dvb_frontend *fe, int onoff)
 {
        return dib8000_set_gpio(fe, 0, 0, onoff);
 }
@@ -1494,8 +1495,8 @@ static const struct dib0070_wbd_gain_cfg dib8070_wbd_gain_cfg[] = {
 static struct dib0070_config dib807x_dib0070_config[2] = {
        {
                .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
-               .reset = dib807x_tuner_reset,
-               .sleep = dib807x_tuner_sleep,
+               .reset = dib80xx_tuner_reset,
+               .sleep = dib80xx_tuner_sleep,
                .clock_khz = 12000,
                .clock_pad_drive = 4,
                .vga_filter = 1,
@@ -1508,8 +1509,8 @@ static struct dib0070_config dib807x_dib0070_config[2] = {
                .freq_offset_khz_vhf = -100,
        }, {
                .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
-               .reset = dib807x_tuner_reset,
-               .sleep = dib807x_tuner_sleep,
+               .reset = dib80xx_tuner_reset,
+               .sleep = dib80xx_tuner_sleep,
                .clock_khz = 12000,
                .clock_pad_drive = 2,
                .vga_filter = 1,
@@ -1566,12 +1567,12 @@ static int dib807x_tuner_attach(struct dvb_usb_adapter *adap)
        return 0;
 }
 
-static int stk807x_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff)
+static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff)
 {
     return dib8000_pid_filter(adapter->fe, index, pid, onoff);
 }
 
-static int stk807x_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
+static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
 {
     return dib8000_pid_filter_ctrl(adapter->fe, onoff);
 }
@@ -1643,6 +1644,246 @@ static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap)
        return adap->fe == NULL ? -ENODEV : 0;
 }
 
+/* STK8096GP */
+struct dibx000_agc_config dib8090_agc_config[2] = {
+    {
+       BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
+       /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
+        * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
+       (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup
+
+       787,// inv_gain = 1/ 90.4dB // no boost, lower gain due to ramp quantification
+       10,  // time_stabiliz
+
+       0,  // alpha_level
+       118,  // thlock
+
+       0,     // wbd_inv
+       3530,  // wbd_ref
+       1,     // wbd_sel
+       5,     // wbd_alpha
+
+       65535,  // agc1_max
+       0,  // agc1_min
+
+       65535,  // agc2_max
+       0,      // agc2_min
+
+       0,      // agc1_pt1
+       32,     // agc1_pt2
+       114,    // agc1_pt3  // 40.4dB
+       143,    // agc1_slope1
+       144,    // agc1_slope2
+       114,    // agc2_pt1
+       227,    // agc2_pt2
+       116,    // agc2_slope1
+       117,    // agc2_slope2
+
+       28,  // alpha_mant // 5Hz with 90.2dB
+       26,  // alpha_exp
+       31,  // beta_mant
+       51,  // beta_exp
+
+       0,  // perform_agc_softsplit
+    },
+    {
+       BAND_CBAND,
+       /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
+        * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
+       (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup
+
+       787,// inv_gain = 1/ 90.4dB // no boost, lower gain due to ramp quantification
+       10,  // time_stabiliz
+
+       0,  // alpha_level
+       118,  // thlock
+
+       0,     // wbd_inv
+       3530,  // wbd_ref
+       1,     // wbd_sel
+       5,     // wbd_alpha
+
+       0,  // agc1_max
+       0,  // agc1_min
+
+       65535,  // agc2_max
+       0,      // agc2_min
+
+       0,      // agc1_pt1
+       32,     // agc1_pt2
+       114,    // agc1_pt3  // 40.4dB
+       143,    // agc1_slope1
+       144,    // agc1_slope2
+       114,    // agc2_pt1
+       227,    // agc2_pt2
+       116,    // agc2_slope1
+       117,    // agc2_slope2
+
+       28,  // alpha_mant // 5Hz with 90.2dB
+       26,  // alpha_exp
+       31,  // beta_mant
+       51,  // beta_exp
+
+       0,  // perform_agc_softsplit
+    }
+};
+
+static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = {
+    54000, 13500, // internal, sampling
+    1, 18, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass
+    0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo
+    (3 << 14) | (1 << 12) | (599 << 0), // sad_cfg: refsel, sel, freq_15k
+    (0 << 25) | 0, // ifreq = 0 MHz
+    20199727, // timf
+    12000000, // xtal_hz
+};
+
+static int dib8090_get_adc_power(struct dvb_frontend *fe)
+{
+    return dib8000_get_adc_power(fe, 1);
+}
+
+static struct dib8000_config dib809x_dib8000_config = {
+    .output_mpeg2_in_188_bytes = 1,
+
+    .agc_config_count = 2,
+    .agc = dib8090_agc_config,
+    .agc_control = dib0090_dcc_freq,
+    .pll = &dib8090_pll_config_12mhz,
+    .tuner_is_baseband = 1,
+
+    .gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS,
+    .gpio_val = DIB8000_GPIO_DEFAULT_VALUES,
+    .gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS,
+
+    .hostbus_diversity = 1,
+    .div_cfg = 0x31,
+    .output_mode = OUTMODE_MPEG2_FIFO,
+    .drives = 0x2d98,
+    .diversity_delay = 144,
+    .refclksel = 3,
+};
+
+static struct dib0090_config dib809x_dib0090_config = {
+    .io.pll_bypass = 1,
+    .io.pll_range = 1,
+    .io.pll_prediv = 1,
+    .io.pll_loopdiv = 20,
+    .io.adc_clock_ratio = 8,
+    .io.pll_int_loop_filt = 0,
+    .io.clock_khz = 12000,
+    .reset = dib80xx_tuner_reset,
+    .sleep = dib80xx_tuner_sleep,
+    .clkouttobamse = 1,
+    .analog_output = 1,
+    .i2c_address = DEFAULT_DIB0090_I2C_ADDRESS,
+    .wbd_vhf_offset = 100,
+    .wbd_cband_offset = 450,
+    .use_pwm_agc = 1,
+    .clkoutdrive = 1,
+    .get_adc_power = dib8090_get_adc_power,
+       .freq_offset_khz_uhf = 0,
+       .freq_offset_khz_vhf = -143,
+};
+
+static int dib8096_set_param_override(struct dvb_frontend *fe,
+               struct dvb_frontend_parameters *fep)
+{
+    struct dvb_usb_adapter *adap = fe->dvb->priv;
+    struct dib0700_adapter_state *state = adap->priv;
+    u8 band = BAND_OF_FREQUENCY(fep->frequency/1000);
+    u16 offset;
+    int ret = 0;
+    enum frontend_tune_state tune_state = CT_SHUTDOWN;
+    u16 ltgain, rf_gain_limit;
+
+    ret = state->set_param_save(fe, fep);
+    if (ret < 0)
+       return ret;
+
+    switch (band) {
+       case BAND_VHF:
+           offset = 100;
+           break;
+       case BAND_UHF:
+           offset = 550;
+           break;
+       default:
+           offset = 0;
+           break;
+    }
+    offset += (dib0090_get_wbd_offset(fe) * 8 * 18 / 33 + 1) / 2;
+    dib8000_set_wbd_ref(fe, offset);
+
+
+    if (band == BAND_CBAND)
+    {
+       deb_info("tuning in CBAND - soft-AGC startup\n");
+       /* TODO specific wbd target for dib0090 - needed for startup ? */
+       dib0090_set_tune_state(fe, CT_AGC_START);
+       do
+       {
+           ret = dib0090_gain_control(fe);
+           msleep(ret);
+           tune_state = dib0090_get_tune_state(fe);
+           if (tune_state == CT_AGC_STEP_0)
+               dib8000_set_gpio(fe, 6, 0, 1);
+           else if (tune_state == CT_AGC_STEP_1)
+           {
+               dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
+               if (rf_gain_limit == 0)
+                   dib8000_set_gpio(fe, 6, 0, 0);
+           }
+       }
+       while(tune_state<CT_AGC_STOP);
+       dib0090_pwm_gain_reset(fe);
+       dib8000_pwm_agc_reset(fe);
+       dib8000_set_tune_state(fe, CT_DEMOD_START);
+    }
+    else {
+       deb_info("not tuning in CBAND - standard AGC startup\n");
+       dib0090_pwm_gain_reset(fe);
+    }
+
+    return 0;
+}
+
+static int dib809x_tuner_attach(struct dvb_usb_adapter *adap)
+{
+    struct dib0700_adapter_state *st = adap->priv;
+    struct i2c_adapter *tun_i2c = dib8000_get_i2c_master(adap->fe, DIBX000_I2C_INTERFACE_TUNER, 1);
+
+    if (dvb_attach(dib0090_register, adap->fe, tun_i2c, &dib809x_dib0090_config) == NULL)
+       return -ENODEV;
+
+    st->set_param_save = adap->fe->ops.tuner_ops.set_params;
+    adap->fe->ops.tuner_ops.set_params = dib8096_set_param_override;
+    return 0;
+}
+
+static int stk809x_frontend_attach(struct dvb_usb_adapter *adap)
+{
+       dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
+       msleep(10);
+       dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
+       dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
+       dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
+
+       dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
+
+       dib0700_ctrl_clock(adap->dev, 72, 1);
+
+       msleep(10);
+       dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
+       msleep(10);
+       dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
+
+       dib8000_i2c_enumeration(&adap->dev->i2c_adap, 1, 18, 0x80);
+
+       adap->fe = dvb_attach(dib8000_attach, &adap->dev->i2c_adap, 0x80, &dib809x_dib8000_config);
+
+       return adap->fe == NULL ?  -ENODEV : 0;
+}
 
 /* STK7070PD */
 static struct dib7000p_config stk7070pd_dib7000p_config[2] = {
@@ -1939,6 +2180,7 @@ struct usb_device_id dib0700_usb_id_table[] = {
        { USB_DEVICE(USB_VID_EVOLUTEPC, USB_PID_TVWAY_PLUS) },
 /* 65 */{ USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV73ESE) },
        { USB_DEVICE(USB_VID_PINNACLE,  USB_PID_PINNACLE_PCTV282E) },
+       { USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK8096GP) },
        { 0 }           /* Terminating entry */
 };
 MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
@@ -2473,8 +2715,8 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                        {
                                .caps  = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
                                .pid_filter_count = 32,
-                               .pid_filter = stk807x_pid_filter,
-                               .pid_filter_ctrl = stk807x_pid_filter_ctrl,
+                               .pid_filter = stk80xx_pid_filter,
+                               .pid_filter_ctrl = stk80xx_pid_filter_ctrl,
                                .frontend_attach  = stk807x_frontend_attach,
                                .tuner_attach     = dib807x_tuner_attach,
 
@@ -2512,8 +2754,8 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                        {
                                .caps  = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
                                .pid_filter_count = 32,
-                               .pid_filter = stk807x_pid_filter,
-                               .pid_filter_ctrl = stk807x_pid_filter_ctrl,
+                               .pid_filter = stk80xx_pid_filter,
+                               .pid_filter_ctrl = stk80xx_pid_filter_ctrl,
                                .frontend_attach  = stk807xpvr_frontend_attach0,
                                .tuner_attach     = dib807x_tuner_attach,
 
@@ -2525,8 +2767,8 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                        {
                                .caps  = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
                                .pid_filter_count = 32,
-                               .pid_filter = stk807x_pid_filter,
-                               .pid_filter_ctrl = stk807x_pid_filter_ctrl,
+                               .pid_filter = stk80xx_pid_filter,
+                               .pid_filter_ctrl = stk80xx_pid_filter_ctrl,
                                .frontend_attach  = stk807xpvr_frontend_attach1,
                                .tuner_attach     = dib807x_tuner_attach,
 
@@ -2545,6 +2787,37 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                        },
                },
 
+               .rc_interval      = DEFAULT_RC_INTERVAL,
+               .rc_key_map       = dib0700_rc_keys,
+               .rc_key_map_size  = ARRAY_SIZE(dib0700_rc_keys),
+               .rc_query         = dib0700_rc_query
+       }, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
+               .num_adapters = 1,
+               .adapter = {
+                       {
+                               .caps  = DVB_USB_ADAP_HAS_PID_FILTER |
+                                       DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+                               .pid_filter_count = 32,
+                               .pid_filter = stk80xx_pid_filter,
+                               .pid_filter_ctrl = stk80xx_pid_filter_ctrl,
+                               .frontend_attach  = stk809x_frontend_attach,
+                               .tuner_attach     = dib809x_tuner_attach,
+
+                               DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
+
+                               .size_of_priv =
+                                       sizeof(struct dib0700_adapter_state),
+                       },
+               },
+
+               .num_device_descs = 1,
+               .devices = {
+                       {   "DiBcom STK8096GP reference design",
+                               { &dib0700_usb_id_table[67], NULL },
+                               { NULL },
+                       },
+               },
+
                .rc_interval      = DEFAULT_RC_INTERVAL,
                .rc_key_map       = dib0700_rc_keys,
                .rc_key_map_size  = ARRAY_SIZE(dib0700_rc_keys),
index cf7f2b4b75eab5a5043b03ebe12117d5ae4f461a..bc3581d58cedb8be3afe98555d8d5e1544ea8406 100644 (file)
 #define USB_PID_DIBCOM_STK7070PD                       0x1ebe
 #define USB_PID_DIBCOM_STK807XP                                0x1f90
 #define USB_PID_DIBCOM_STK807XPVR                      0x1f98
+#define USB_PID_DIBCOM_STK8096GP                        0x1fa0
 #define USB_PID_DIBCOM_ANCHOR_2135_COLD                        0x2131
 #define USB_PID_DIBCOM_STK7770P                                0x1e80
 #define USB_PID_DPOSH_M9206_COLD                       0x9206
index 58aac018f109003aaea23322ac22804d8b52020c..a3b8b697349b130f161daf1dc747d40c89ffcdb7 100644 (file)
@@ -526,6 +526,15 @@ config DVB_TUNER_DIB0070
          This device is only used inside a SiP called together with a
          demodulator for now.
 
+config DVB_TUNER_DIB0090
+       tristate "DiBcom DiB0090 silicon base-band tuner"
+       depends on I2C
+       default m if DVB_FE_CUSTOMISE
+       help
+         A driver for the silicon baseband tuner DiB0090 from DiBcom.
+         This device is only used inside a SiP called together with a
+         demodulator for now.
+
 comment "SEC control devices for DVB-S"
        depends on DVB_CORE
 
index 823482535d110000b2d9a9c61508b3e1da813ec6..47575cc7b699cea3a431b6d1c29093847402a5e8 100644 (file)
@@ -55,6 +55,7 @@ obj-$(CONFIG_DVB_TDA10086) += tda10086.o
 obj-$(CONFIG_DVB_TDA826X) += tda826x.o
 obj-$(CONFIG_DVB_TDA8261) += tda8261.o
 obj-$(CONFIG_DVB_TUNER_DIB0070) += dib0070.o
+obj-$(CONFIG_DVB_TUNER_DIB0090) += dib0090.o
 obj-$(CONFIG_DVB_TUA6100) += tua6100.o
 obj-$(CONFIG_DVB_S5H1409) += s5h1409.o
 obj-$(CONFIG_DVB_TUNER_ITD1000) += itd1000.o
index 2be17b93e0bd7dcf2419b263316971304f30072f..81860b2cfe98aef04ca69f59c1f0d7865884d780 100644 (file)
@@ -49,21 +49,6 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
 #define DIB0070_P1G  0x03
 #define DIB0070S_P1A 0x02
 
-enum frontend_tune_state {
-       CT_TUNER_START = 10,
-       CT_TUNER_STEP_0,
-       CT_TUNER_STEP_1,
-       CT_TUNER_STEP_2,
-       CT_TUNER_STEP_3,
-       CT_TUNER_STEP_4,
-       CT_TUNER_STEP_5,
-       CT_TUNER_STEP_6,
-       CT_TUNER_STEP_7,
-       CT_TUNER_STOP,
-};
-
-#define FE_CALLBACK_TIME_NEVER 0xffffffff
-
 struct dib0070_state {
        struct i2c_adapter *i2c;
        struct dvb_frontend *fe;
@@ -71,10 +56,10 @@ struct dib0070_state {
        u16 wbd_ff_offset;
        u8 revision;
 
-       enum frontend_tune_state tune_state;
-       u32 current_rf;
+    enum frontend_tune_state tune_state;
+    u32 current_rf;
 
-       /* for the captrim binary search */
+    /* for the captrim binary search */
        s8 step;
        u16 adc_diff;
 
@@ -85,7 +70,7 @@ struct dib0070_state {
        const struct dib0070_tuning *current_tune_table_index;
        const struct dib0070_lna_match *lna_match;
 
-       u8 wbd_gain_current;
+    u8  wbd_gain_current;
        u16 wbd_offset_3_3[2];
 };
 
@@ -93,8 +78,8 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
 {
        u8 b[2];
        struct i2c_msg msg[2] = {
-               {.addr = state->cfg->i2c_address,.flags = 0,.buf = &reg,.len = 1},
-               {.addr = state->cfg->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2},
+               { .addr = state->cfg->i2c_address, .flags = 0,        .buf = &reg, .len = 1 },
+               { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = b,  .len = 2 },
        };
        if (i2c_transfer(state->i2c, msg, 2) != 2) {
                printk(KERN_WARNING "DiB0070 I2C read failed\n");
@@ -106,7 +91,7 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
 static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
 {
        u8 b[3] = { reg, val >> 8, val & 0xff };
-       struct i2c_msg msg = {.addr = state->cfg->i2c_address,.flags = 0,.buf = b,.len = 3 };
+       struct i2c_msg msg = { .addr = state->cfg->i2c_address, .flags = 0, .buf = b, .len = 3 };
        if (i2c_transfer(state->i2c, &msg, 1) != 1) {
                printk(KERN_WARNING "DiB0070 I2C write failed\n");
                return -EREMOTEIO;
@@ -124,30 +109,30 @@ static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
 
 static int dib0070_set_bandwidth(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
 {
-       struct dib0070_state *state = fe->tuner_priv;
-       u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
-
-       if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 7000)
-               tmp |= (0 << 14);
-       else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 6000)
-               tmp |= (1 << 14);
-       else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 5000)
-               tmp |= (2 << 14);
-       else
-               tmp |= (3 << 14);
-
-       dib0070_write_reg(state, 0x02, tmp);
-
-       /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
-       if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
-               u16 value = dib0070_read_reg(state, 0x17);
-
-               dib0070_write_reg(state, 0x17, value & 0xfffc);
-               tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
-               dib0070_write_reg(state, 0x01, tmp | (60 << 9));
-
-               dib0070_write_reg(state, 0x17, value);
-       }
+    struct dib0070_state *state = fe->tuner_priv;
+    u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
+
+    if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 7000)
+       tmp |= (0 << 14);
+    else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 6000)
+       tmp |= (1 << 14);
+    else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 5000)
+       tmp |= (2 << 14);
+    else
+       tmp |= (3 << 14);
+
+    dib0070_write_reg(state, 0x02, tmp);
+
+    /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
+    if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
+       u16 value = dib0070_read_reg(state, 0x17);
+
+       dib0070_write_reg(state, 0x17, value & 0xfffc);
+       tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
+       dib0070_write_reg(state, 0x01, tmp | (60 << 9));
+
+       dib0070_write_reg(state, 0x17, value);
+    }
        return 0;
 }
 
@@ -160,14 +145,14 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
        if (*tune_state == CT_TUNER_STEP_0) {
 
                dib0070_write_reg(state, 0x0f, 0xed10);
-               dib0070_write_reg(state, 0x17, 0x0034);
+               dib0070_write_reg(state, 0x17,    0x0034);
 
                dib0070_write_reg(state, 0x18, 0x0032);
                state->step = state->captrim = state->fcaptrim = 64;
                state->adc_diff = 3000;
                ret = 20;
 
-               *tune_state = CT_TUNER_STEP_1;
+       *tune_state = CT_TUNER_STEP_1;
        } else if (*tune_state == CT_TUNER_STEP_1) {
                state->step /= 2;
                dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
@@ -178,7 +163,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
 
                adc = dib0070_read_reg(state, 0x19);
 
-               dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc * (u32) 1800 / (u32) 1024);
+               dprintk( "CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024);
 
                if (adc >= 400) {
                        adc -= 400;
@@ -189,10 +174,12 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
                }
 
                if (adc < state->adc_diff) {
-                       dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff);
+                       dprintk( "CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff);
                        state->adc_diff = adc;
                        state->fcaptrim = state->captrim;
 
+
+
                }
                state->captrim += (step_sign * state->step);
 
@@ -213,8 +200,8 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state
 static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
 {
        struct dib0070_state *state = fe->tuner_priv;
-       u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
-       dprintk("CTRL_LO5: 0x%x", lo5);
+    u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
+       dprintk( "CTRL_LO5: 0x%x", lo5);
        return dib0070_write_reg(state, 0x15, lo5);
 }
 
@@ -227,171 +214,175 @@ void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
                dib0070_write_reg(state, 0x1a, 0x0000);
        } else {
                dib0070_write_reg(state, 0x1b, 0x4112);
-               if (state->cfg->vga_filter != 0) {
-                       dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
-                       dprintk("vga filter register is set to %x", state->cfg->vga_filter);
-               } else
-                       dib0070_write_reg(state, 0x1a, 0x0009);
+       if (state->cfg->vga_filter != 0) {
+           dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
+           dprintk( "vga filter register is set to %x", state->cfg->vga_filter);
+       } else
+           dib0070_write_reg(state, 0x1a, 0x0009);
        }
 }
 
 EXPORT_SYMBOL(dib0070_ctrl_agc_filter);
 struct dib0070_tuning {
-       u32 max_freq;           /* for every frequency less than or equal to that field: this information is correct */
-       u8 switch_trim;
-       u8 vco_band;
-       u8 hfdiv;
-       u8 vco_multi;
-       u8 presc;
-       u8 wbdmux;
-       u16 tuner_enable;
+    u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
+    u8 switch_trim;
+    u8 vco_band;
+    u8 hfdiv;
+    u8 vco_multi;
+    u8 presc;
+    u8 wbdmux;
+    u16 tuner_enable;
 };
 
 struct dib0070_lna_match {
-       u32 max_freq;           /* for every frequency less than or equal to that field: this information is correct */
-       u8 lna_band;
+    u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
+    u8 lna_band;
 };
 
 static const struct dib0070_tuning dib0070s_tuning_table[] = {
-       {570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800},    /* UHF */
-       {700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800},
-       {863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800},
-       {1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},   /* LBAND */
-       {1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},
-       {2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},
-       {0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000},        /* SBAND */
+    {     570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800 }, /* UHF */
+    {     700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800 },
+    {     863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800 },
+    {    1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND */
+    {    1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
+    {    2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
+    { 0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000 }, /* SBAND */
 };
 
 static const struct dib0070_tuning dib0070_tuning_table[] = {
-       {115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000},   /* FM below 92MHz cannot be tuned */
-       {179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000},   /* VHF */
-       {189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000},
-       {250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000},
-       {569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800},    /* UHF */
-       {699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800},
-       {863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800},
-       {0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400},        /* LBAND or everything higher than UHF */
+    {     115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000 }, /* FM below 92MHz cannot be tuned */
+    {     179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000 }, /* VHF */
+    {     189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
+    {     250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
+    {     569999, 2, 1, 5,  6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
+    {     699999, 2, 0 ,1,  4, 2, 2, 0x4000 | 0x0800 },
+    {     863999, 2, 1, 1,  4, 2, 2, 0x4000 | 0x0800 },
+    { 0xffffffff, 0, 1, 0,  2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
 };
 
 static const struct dib0070_lna_match dib0070_lna_flip_chip[] = {
-       {180000, 0},            /* VHF */
-       {188000, 1},
-       {196400, 2},
-       {250000, 3},
-       {550000, 0},            /* UHF */
-       {590000, 1},
-       {666000, 3},
-       {864000, 5},
-       {1500000, 0},           /* LBAND or everything higher than UHF */
-       {1600000, 1},
-       {2000000, 3},
-       {0xffffffff, 7},
+    {     180000, 0 }, /* VHF */
+    {     188000, 1 },
+    {     196400, 2 },
+    {     250000, 3 },
+    {     550000, 0 }, /* UHF */
+    {     590000, 1 },
+    {     666000, 3 },
+    {     864000, 5 },
+    {    1500000, 0 }, /* LBAND or everything higher than UHF */
+    {    1600000, 1 },
+    {    2000000, 3 },
+    { 0xffffffff, 7 },
 };
 
 static const struct dib0070_lna_match dib0070_lna[] = {
-       {180000, 0},            /* VHF */
-       {188000, 1},
-       {196400, 2},
-       {250000, 3},
-       {550000, 2},            /* UHF */
-       {650000, 3},
-       {750000, 5},
-       {850000, 6},
-       {864000, 7},
-       {1500000, 0},           /* LBAND or everything higher than UHF */
-       {1600000, 1},
-       {2000000, 3},
-       {0xffffffff, 7},
+    {     180000, 0 }, /* VHF */
+    {     188000, 1 },
+    {     196400, 2 },
+    {     250000, 3 },
+    {     550000, 2 }, /* UHF */
+    {     650000, 3 },
+    {     750000, 5 },
+    {     850000, 6 },
+    {     864000, 7 },
+    {    1500000, 0 }, /* LBAND or everything higher than UHF */
+    {    1600000, 1 },
+    {    2000000, 3 },
+    { 0xffffffff, 7 },
 };
 
-#define LPF    100             // define for the loop filter 100kHz by default 16-07-06
+#define LPF    100                       // define for the loop filter 100kHz by default 16-07-06
 static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
 {
-       struct dib0070_state *state = fe->tuner_priv;
+    struct dib0070_state *state = fe->tuner_priv;
 
-       const struct dib0070_tuning *tune;
-       const struct dib0070_lna_match *lna_match;
+    const struct dib0070_tuning *tune;
+    const struct dib0070_lna_match *lna_match;
 
-       enum frontend_tune_state *tune_state = &state->tune_state;
-       int ret = 10;           /* 1ms is the default delay most of the time */
+    enum frontend_tune_state *tune_state = &state->tune_state;
+    int ret = 10; /* 1ms is the default delay most of the time */
 
-       u8 band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
-       u32 freq = fe->dtv_property_cache.frequency / 1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
+    u8  band = (u8)BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency/1000);
+    u32 freq = fe->dtv_property_cache.frequency/1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
 
 #ifdef CONFIG_SYS_ISDBT
-       if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
+    if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
                if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
                     && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
                    || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
                        && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
                    || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
                        && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
-                       freq += 850;
+           freq += 850;
 #endif
+    if (state->current_rf != freq) {
+
+       switch (state->revision) {
+       case DIB0070S_P1A:
+           tune = dib0070s_tuning_table;
+           lna_match = dib0070_lna;
+           break;
+       default:
+           tune = dib0070_tuning_table;
+           if (state->cfg->flip_chip)
+               lna_match = dib0070_lna_flip_chip;
+           else
+               lna_match = dib0070_lna;
+           break;
+       }
+       while (freq > tune->max_freq) /* find the right one */
+           tune++;
+       while (freq > lna_match->max_freq) /* find the right one */
+           lna_match++;
+
+       state->current_tune_table_index = tune;
+       state->lna_match = lna_match;
+    }
+
+    if (*tune_state == CT_TUNER_START) {
+       dprintk( "Tuning for Band: %hd (%d kHz)", band, freq);
        if (state->current_rf != freq) {
+           u8 REFDIV;
+           u32 FBDiv, Rest, FREF, VCOF_kHz;
+           u8 Den;
 
-               switch (state->revision) {
-               case DIB0070S_P1A:
-                       tune = dib0070s_tuning_table;
-                       lna_match = dib0070_lna;
-                       break;
-               default:
-                       tune = dib0070_tuning_table;
-                       if (state->cfg->flip_chip)
-                               lna_match = dib0070_lna_flip_chip;
-                       else
-                               lna_match = dib0070_lna;
-                       break;
-               }
-               while (freq > tune->max_freq)   /* find the right one */
-                       tune++;
-               while (freq > lna_match->max_freq)      /* find the right one */
-                       lna_match++;
+           state->current_rf = freq;
+           state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
 
-               state->current_tune_table_index = tune;
-               state->lna_match = lna_match;
-       }
 
-       if (*tune_state == CT_TUNER_START) {
-               dprintk("Tuning for Band: %hd (%d kHz)", band, freq);
-               if (state->current_rf != freq) {
-                       u8 REFDIV;
-                       u32 FBDiv, Rest, FREF, VCOF_kHz;
-                       u8 Den;
-
-                       state->current_rf = freq;
-                       state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
-
-                       dib0070_write_reg(state, 0x17, 0x30);
-
-                       VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
-
-                       switch (band) {
-                       case BAND_VHF:
-                               REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
-                               break;
-                       case BAND_FM:
-                               REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
-                               break;
-                       default:
-                               REFDIV = (u8) (state->cfg->clock_khz / 10000);
-                               break;
-                       }
-                       FREF = state->cfg->clock_khz / REFDIV;
-
-                       switch (state->revision) {
-                       case DIB0070S_P1A:
-                               FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
-                               Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
-                               break;
-
-                       case DIB0070_P1G:
-                       case DIB0070_P1F:
-                       default:
-                               FBDiv = (freq / (FREF / 2));
-                               Rest = 2 * freq - FBDiv * FREF;
-                               break;
-                       }
+           dib0070_write_reg(state, 0x17, 0x30);
+
+
+           VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
+
+           switch (band) {
+           case BAND_VHF:
+               REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
+               break;
+           case BAND_FM:
+               REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
+               break;
+           default:
+               REFDIV = (u8) ( state->cfg->clock_khz  / 10000);
+               break;
+           }
+           FREF = state->cfg->clock_khz / REFDIV;
+
+
+
+           switch (state->revision) {
+           case DIB0070S_P1A:
+               FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
+               Rest  = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
+               break;
+
+           case DIB0070_P1G:
+           case DIB0070_P1F:
+           default:
+               FBDiv = (freq / (FREF / 2));
+               Rest  = 2 * freq - FBDiv * FREF;
+               break;
+           }
 
                        if (Rest < LPF)
                                Rest = 0;
@@ -402,98 +393,102 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par
                                FBDiv += 1;
                        } else if (Rest > (FREF - 2 * LPF))
                                Rest = FREF - 2 * LPF;
-                       Rest = (Rest * 6528) / (FREF / 10);
+           Rest = (Rest * 6528) / (FREF / 10);
 
-                       Den = 1;
-                       if (Rest > 0) {
-                               state->lo4 |= (1 << 14) | (1 << 12);
-                               Den = 255;
-                       }
+           Den = 1;
+           if (Rest > 0) {
+               state->lo4 |= (1 << 14) | (1 << 12);
+               Den = 255;
+           }
 
-                       dib0070_write_reg(state, 0x11, (u16) FBDiv);
-                       dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
-                       dib0070_write_reg(state, 0x13, (u16) Rest);
 
-                       if (state->revision == DIB0070S_P1A) {
+           dib0070_write_reg(state, 0x11, (u16)FBDiv);
+           dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
+           dib0070_write_reg(state, 0x13, (u16) Rest);
 
-                               if (band == BAND_SBAND) {
-                                       dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
-                                       dib0070_write_reg(state, 0x1d, 0xFFFF);
-                               } else
-                                       dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
-                       }
+           if (state->revision == DIB0070S_P1A) {
+
+               if (band == BAND_SBAND) {
+                   dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
+                   dib0070_write_reg(state, 0x1d,0xFFFF);
+               } else
+                   dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
+           }
 
                        dib0070_write_reg(state, 0x20,
                                          0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
 
-                       dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF);
-                       dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest);
-                       dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
-                       dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv);
-                       dprintk("VCO = %hd", state->current_tune_table_index->vco_band);
-                       dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
-
-                       *tune_state = CT_TUNER_STEP_0;
-               } else {        /* we are already tuned to this frequency - the configuration is correct  */
-                       ret = 50;       /* wakeup time */
-                       *tune_state = CT_TUNER_STEP_5;
-               }
-       } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
+           dprintk( "REFDIV: %hd, FREF: %d", REFDIV, FREF);
+           dprintk( "FBDIV: %d, Rest: %d", FBDiv, Rest);
+           dprintk( "Num: %hd, Den: %hd, SD: %hd",(u16) Rest, Den, (state->lo4 >> 12) & 0x1);
+           dprintk( "HFDIV code: %hd", state->current_tune_table_index->hfdiv);
+           dprintk( "VCO = %hd", state->current_tune_table_index->vco_band);
+           dprintk( "VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
+
+           *tune_state = CT_TUNER_STEP_0;
+       } else { /* we are already tuned to this frequency - the configuration is correct  */
+           ret = 50; /* wakeup time */
+           *tune_state = CT_TUNER_STEP_5;
+       }
+    } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
 
-               ret = dib0070_captrim(state, tune_state);
+       ret = dib0070_captrim(state, tune_state);
 
-       } else if (*tune_state == CT_TUNER_STEP_4) {
-               const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
-               if (tmp != NULL) {
-                       while (freq / 1000 > tmp->freq) /* find the right one */
-                               tmp++;
+    } else if (*tune_state == CT_TUNER_STEP_4) {
+       const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
+       if (tmp != NULL) {
+           while (freq/1000 > tmp->freq) /* find the right one */
+               tmp++;
                        dib0070_write_reg(state, 0x0f,
                                          (0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state->
                                                                                                                                current_tune_table_index->
                                                                                                                                wbdmux << 0));
-                       state->wbd_gain_current = tmp->wbd_gain_val;
-               } else {
+           state->wbd_gain_current = tmp->wbd_gain_val;
+       } else {
                        dib0070_write_reg(state, 0x0f,
                                          (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index->
                                                                                                                wbdmux << 0));
-                       state->wbd_gain_current = 6;
-               }
+           state->wbd_gain_current = 6;
+       }
 
-               dib0070_write_reg(state, 0x06, 0x3fff);
+       dib0070_write_reg(state, 0x06, 0x3fff);
                dib0070_write_reg(state, 0x07,
                                  (state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
-               dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
-               dib0070_write_reg(state, 0x0d, 0x0d80);
+       dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
+       dib0070_write_reg(state, 0x0d, 0x0d80);
 
-               dib0070_write_reg(state, 0x18, 0x07ff);
-               dib0070_write_reg(state, 0x17, 0x0033);
 
-               *tune_state = CT_TUNER_STEP_5;
-       } else if (*tune_state == CT_TUNER_STEP_5) {
-               dib0070_set_bandwidth(fe, ch);
-               *tune_state = CT_TUNER_STOP;
-       } else {
-               ret = FE_CALLBACK_TIME_NEVER;   /* tuner finished, time to call again infinite */
-       }
-       return ret;
+       dib0070_write_reg(state, 0x18,   0x07ff);
+       dib0070_write_reg(state, 0x17, 0x0033);
+
+
+       *tune_state = CT_TUNER_STEP_5;
+    } else if (*tune_state == CT_TUNER_STEP_5) {
+       dib0070_set_bandwidth(fe, ch);
+       *tune_state = CT_TUNER_STOP;
+    } else {
+       ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
+    }
+    return ret;
 }
 
+
 static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
 {
-       struct dib0070_state *state = fe->tuner_priv;
-       uint32_t ret;
+    struct dib0070_state *state = fe->tuner_priv;
+    uint32_t ret;
 
-       state->tune_state = CT_TUNER_START;
+    state->tune_state = CT_TUNER_START;
 
-       do {
-               ret = dib0070_tune_digital(fe, p);
-               if (ret != FE_CALLBACK_TIME_NEVER)
-                       msleep(ret / 10);
-               else
-                       break;
-       } while (state->tune_state != CT_TUNER_STOP);
+    do {
+       ret = dib0070_tune_digital(fe, p);
+       if (ret != FE_CALLBACK_TIME_NEVER)
+           msleep(ret/10);
+       else
+           break;
+    } while (state->tune_state != CT_TUNER_STOP);
 
-       return 0;
+    return 0;
 }
 
 static int dib0070_wakeup(struct dvb_frontend *fe)
@@ -512,92 +507,111 @@ static int dib0070_sleep(struct dvb_frontend *fe)
        return 0;
 }
 
-static const u16 dib0070_p1f_defaults[] = {
+u8 dib0070_get_rf_output(struct dvb_frontend *fe)
+{
+       struct dib0070_state *state = fe->tuner_priv;
+       return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
+}
+
+EXPORT_SYMBOL(dib0070_get_rf_output);
+int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
+{
+       struct dib0070_state *state = fe->tuner_priv;
+       u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
+       if (no > 3) no = 3;
+       if (no < 1) no = 1;
+       return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
+}
+
+EXPORT_SYMBOL(dib0070_set_rf_output);
+static const u16 dib0070_p1f_defaults[] =
+
+{
        7, 0x02,
-       0x0008,
-       0x0000,
-       0x0000,
-       0x0000,
-       0x0000,
-       0x0002,
-       0x0100,
+               0x0008,
+               0x0000,
+               0x0000,
+               0x0000,
+               0x0000,
+               0x0002,
+               0x0100,
 
        3, 0x0d,
-       0x0d80,
-       0x0001,
-       0x0000,
+               0x0d80,
+               0x0001,
+               0x0000,
 
        4, 0x11,
-       0x0000,
-       0x0103,
-       0x0000,
-       0x0000,
+               0x0000,
+               0x0103,
+               0x0000,
+               0x0000,
 
        3, 0x16,
-       0x0004 | 0x0040,
-       0x0030,
-       0x07ff,
+               0x0004 | 0x0040,
+               0x0030,
+               0x07ff,
 
        6, 0x1b,
-       0x4112,
-       0xff00,
-       0xc07f,
-       0x0000,
-       0x0180,
-       0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
+               0x4112,
+               0xff00,
+               0xc07f,
+               0x0000,
+               0x0180,
+               0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
 
        0,
 };
 
 static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
 {
-       u16 tuner_en = dib0070_read_reg(state, 0x20);
-       u16 offset;
-
-       dib0070_write_reg(state, 0x18, 0x07ff);
-       dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
-       dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
-       msleep(9);
-       offset = dib0070_read_reg(state, 0x19);
-       dib0070_write_reg(state, 0x20, tuner_en);
-       return offset;
+    u16 tuner_en = dib0070_read_reg(state, 0x20);
+    u16 offset;
+
+    dib0070_write_reg(state, 0x18, 0x07ff);
+    dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
+    dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
+    msleep(9);
+    offset = dib0070_read_reg(state, 0x19);
+    dib0070_write_reg(state, 0x20, tuner_en);
+    return offset;
 }
 
 static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
 {
-       u8 gain;
-       for (gain = 6; gain < 8; gain++) {
-               state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
-               dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain - 6]);
-       }
+    u8 gain;
+    for (gain = 6; gain < 8; gain++) {
+       state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
+       dprintk( "Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]);
+    }
 }
 
 u16 dib0070_wbd_offset(struct dvb_frontend *fe)
 {
-       struct dib0070_state *state = fe->tuner_priv;
-       const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
-       u32 freq = fe->dtv_property_cache.frequency / 1000;
-
-       if (tmp != NULL) {
-               while (freq / 1000 > tmp->freq) /* find the right one */
-                       tmp++;
-               state->wbd_gain_current = tmp->wbd_gain_val;
+    struct dib0070_state *state = fe->tuner_priv;
+    const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
+    u32 freq = fe->dtv_property_cache.frequency/1000;
+
+    if (tmp != NULL) {
+       while (freq/1000 > tmp->freq) /* find the right one */
+           tmp++;
+       state->wbd_gain_current = tmp->wbd_gain_val;
        } else
-               state->wbd_gain_current = 6;
+       state->wbd_gain_current = 6;
 
-       return state->wbd_offset_3_3[state->wbd_gain_current - 6];
+    return state->wbd_offset_3_3[state->wbd_gain_current - 6];
 }
-
 EXPORT_SYMBOL(dib0070_wbd_offset);
 
 #define pgm_read_word(w) (*w)
 static int dib0070_reset(struct dvb_frontend *fe)
 {
-       struct dib0070_state *state = fe->tuner_priv;
+    struct dib0070_state *state = fe->tuner_priv;
        u16 l, r, *n;
 
        HARD_RESET(state);
 
+
 #ifndef FORCE_SBAND_TUNER
        if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
                state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
@@ -605,13 +619,13 @@ static int dib0070_reset(struct dvb_frontend *fe)
 #else
 #warning forcing SBAND
 #endif
-       state->revision = DIB0070S_P1A;
+               state->revision = DIB0070S_P1A;
 
        /* P1F or not */
-       dprintk("Revision: %x", state->revision);
+       dprintk( "Revision: %x", state->revision);
 
        if (state->revision == DIB0070_P1D) {
-               dprintk("Error: this driver is not to be used meant for P1D or earlier");
+               dprintk( "Error: this driver is not to be used meant for P1D or earlier");
                return -EINVAL;
        }
 
@@ -620,7 +634,7 @@ static int dib0070_reset(struct dvb_frontend *fe)
        while (l) {
                r = pgm_read_word(n++);
                do {
-                       dib0070_write_reg(state, (u8) r, pgm_read_word(n++));
+                       dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
                        r++;
                } while (--l);
                l = pgm_read_word(n++);
@@ -633,6 +647,7 @@ static int dib0070_reset(struct dvb_frontend *fe)
        else
                r = 2;
 
+
        r |= state->cfg->osc_buffer_state << 3;
 
        dib0070_write_reg(state, 0x10, r);
@@ -643,16 +658,24 @@ static int dib0070_reset(struct dvb_frontend *fe)
                dib0070_write_reg(state, 0x02, r | (1 << 5));
        }
 
-       if (state->revision == DIB0070S_P1A)
-               dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
-       else
+    if (state->revision == DIB0070S_P1A)
+       dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
+    else
                dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump, state->cfg->enable_third_order_filter);
 
        dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
 
-       dib0070_wbd_offset_calibration(state);
+    dib0070_wbd_offset_calibration(state);
 
-       return 0;
+    return 0;
+}
+
+static int dib0070_get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+    struct dib0070_state *state = fe->tuner_priv;
+
+    *frequency = 1000 * state->current_rf;
+    return 0;
 }
 
 static int dib0070_release(struct dvb_frontend *fe)
@@ -664,22 +687,22 @@ static int dib0070_release(struct dvb_frontend *fe)
 
 static const struct dvb_tuner_ops dib0070_ops = {
        .info = {
-                .name = "DiBcom DiB0070",
-                .frequency_min = 45000000,
-                .frequency_max = 860000000,
-                .frequency_step = 1000,
-                },
-       .release = dib0070_release,
-
-       .init = dib0070_wakeup,
-       .sleep = dib0070_sleep,
-       .set_params = dib0070_tune,
-
-//      .get_frequency = dib0070_get_frequency,
+               .name           = "DiBcom DiB0070",
+               .frequency_min  =  45000000,
+               .frequency_max  = 860000000,
+               .frequency_step =      1000,
+       },
+       .release       = dib0070_release,
+
+       .init          = dib0070_wakeup,
+       .sleep         = dib0070_sleep,
+       .set_params    = dib0070_tune,
+
+       .get_frequency = dib0070_get_frequency,
 //      .get_bandwidth = dib0070_get_bandwidth
 };
 
-struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
+struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
 {
        struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
        if (state == NULL)
@@ -687,7 +710,7 @@ struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter
 
        state->cfg = cfg;
        state->i2c = i2c;
-       state->fe = fe;
+       state->fe  = fe;
        fe->tuner_priv = state;
 
        if (dib0070_reset(fe) != 0)
@@ -699,12 +722,11 @@ struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter
        fe->tuner_priv = state;
        return fe;
 
- free_mem:
+free_mem:
        kfree(state);
        fe->tuner_priv = NULL;
        return NULL;
 }
-
 EXPORT_SYMBOL(dib0070_attach);
 
 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
index eec9e52ffa753d0454044ca2705697e53b0ca39f..45c31fae3967118c5f6a55ffe6718de54aee2b8a 100644 (file)
@@ -52,6 +52,8 @@ struct dib0070_config {
 extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg);
 extern u16 dib0070_wbd_offset(struct dvb_frontend *);
 extern void dib0070_ctrl_agc_filter(struct dvb_frontend *, u8 open);
+extern u8 dib0070_get_rf_output(struct dvb_frontend *fe);
+extern int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no);
 #else
 static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
 {
@@ -62,7 +64,7 @@ static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struc
 static inline u16 dib0070_wbd_offset(struct dvb_frontend *fe)
 {
        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-       return -ENODEV;
+       return 0;
 }
 
 static inline void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
new file mode 100644 (file)
index 0000000..e37d32d
--- /dev/null
@@ -0,0 +1,1525 @@
+/*
+ * Linux-DVB Driver for DiBcom's DiB0090 base-band RF Tuner.
+ *
+ * Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * This code is more or less generated from another driver, please
+ * excuse some codingstyle oddities.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+
+#include "dvb_frontend.h"
+
+#include "dib0090.h"
+#include "dibx000_common.h"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
+
+#define dprintk(args...) do { \
+       if (debug) { \
+               printk(KERN_DEBUG "DiB0090: "); \
+               printk(args); \
+               printk("\n"); \
+       } \
+} while (0)
+
+#define CONFIG_SYS_ISDBT
+#define CONFIG_BAND_CBAND
+#define CONFIG_BAND_VHF
+#define CONFIG_BAND_UHF
+#define CONFIG_DIB0090_USE_PWM_AGC
+
+#define EN_LNA0      0x8000
+#define EN_LNA1      0x4000
+#define EN_LNA2      0x2000
+#define EN_LNA3      0x1000
+#define EN_MIX0      0x0800
+#define EN_MIX1      0x0400
+#define EN_MIX2      0x0200
+#define EN_MIX3      0x0100
+#define EN_IQADC     0x0040
+#define EN_PLL       0x0020
+#define EN_TX        0x0010
+#define EN_BB        0x0008
+#define EN_LO        0x0004
+#define EN_BIAS      0x0001
+
+#define EN_IQANA     0x0002
+#define EN_DIGCLK    0x0080    /* not in the 0x24 reg, only in 0x1b */
+#define EN_CRYSTAL   0x0002
+
+#define EN_UHF          0x22E9
+#define EN_VHF          0x44E9
+#define EN_LBD          0x11E9
+#define EN_SBD          0x44E9
+#define EN_CAB          0x88E9
+
+#define pgm_read_word(w) (*w)
+
+struct dc_calibration;
+
+struct dib0090_tuning {
+       u32 max_freq;           /* for every frequency less than or equal to that field: this information is correct */
+       u8 switch_trim;
+       u8 lna_tune;
+       u8 lna_bias;
+       u16 v2i;
+       u16 mix;
+       u16 load;
+       u16 tuner_enable;
+};
+
+struct dib0090_pll {
+       u32 max_freq;           /* for every frequency less than or equal to that field: this information is correct */
+       u8 vco_band;
+       u8 hfdiv_code;
+       u8 hfdiv;
+       u8 topresc;
+};
+
+struct dib0090_state {
+       struct i2c_adapter *i2c;
+       struct dvb_frontend *fe;
+       const struct dib0090_config *config;
+
+       u8 current_band;
+       u16 revision;
+       enum frontend_tune_state tune_state;
+       u32 current_rf;
+
+       u16 wbd_offset;
+       s16 wbd_target;         /* in dB */
+
+       s16 rf_gain_limit;      /* take-over-point: where to split between bb and rf gain */
+       s16 current_gain;       /* keeps the currently programmed gain */
+       u8 agc_step;            /* new binary search */
+
+       u16 gain[2];            /* for channel monitoring */
+
+       const u16 *rf_ramp;
+       const u16 *bb_ramp;
+
+       /* for the software AGC ramps */
+       u16 bb_1_def;
+       u16 rf_lt_def;
+       u16 gain_reg[4];
+
+       /* for the captrim/dc-offset search */
+       s8 step;
+       s16 adc_diff;
+       s16 min_adc_diff;
+
+       s8 captrim;
+       s8 fcaptrim;
+
+       const struct dc_calibration *dc;
+       u16 bb6, bb7;
+
+       const struct dib0090_tuning *current_tune_table_index;
+       const struct dib0090_pll *current_pll_table_index;
+
+       u8 tuner_is_tuned;
+       u8 agc_freeze;
+
+       u8 reset;
+};
+
+static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
+{
+       u8 b[2];
+       struct i2c_msg msg[2] = {
+               {.addr = state->config->i2c_address,.flags = 0,.buf = &reg,.len = 1},
+               {.addr = state->config->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2},
+       };
+       if (i2c_transfer(state->i2c, msg, 2) != 2) {
+               printk(KERN_WARNING "DiB0090 I2C read failed\n");
+               return 0;
+       }
+       return (b[0] << 8) | b[1];
+}
+
+static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
+{
+       u8 b[3] = { reg & 0xff, val >> 8, val & 0xff };
+       struct i2c_msg msg = {.addr = state->config->i2c_address,.flags = 0,.buf = b,.len = 3 };
+       if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+               printk(KERN_WARNING "DiB0090 I2C write failed\n");
+               return -EREMOTEIO;
+       }
+       return 0;
+}
+
+#define HARD_RESET(state) do {  if (cfg->reset) {  if (cfg->sleep) cfg->sleep(fe, 0); msleep(10);  cfg->reset(fe, 1); msleep(10);  cfg->reset(fe, 0); msleep(10);  }  } while (0)
+#define ADC_TARGET -220
+#define GAIN_ALPHA 5
+#define WBD_ALPHA 6
+#define LPF    100
+static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c)
+{
+       do {
+               dib0090_write_reg(state, r++, *b++);
+       } while (--c);
+}
+
+static u16 dib0090_identify(struct dvb_frontend *fe)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       u16 v;
+
+       v = dib0090_read_reg(state, 0x1a);
+
+#ifdef FIRMWARE_FIREFLY
+       /* pll is not locked locked */
+       if (!(v & 0x800))
+               dprintk("FE%d : Identification : pll is not yet locked", fe->id);
+#endif
+
+       /* without PLL lock info */
+       v &= 0x3ff;
+       dprintk("P/V: %04x:", v);
+
+       if ((v >> 8) & 0xf)
+               dprintk("FE%d : Product ID = 0x%x : KROSUS", fe->id, (v >> 8) & 0xf);
+       else
+               return 0xff;
+
+       v &= 0xff;
+       if (((v >> 5) & 0x7) == 0x1)
+               dprintk("FE%d : MP001 : 9090/8096", fe->id);
+       else if (((v >> 5) & 0x7) == 0x4)
+               dprintk("FE%d : MP005 : Single Sband", fe->id);
+       else if (((v >> 5) & 0x7) == 0x6)
+               dprintk("FE%d : MP008 : diversity VHF-UHF-LBAND", fe->id);
+       else if (((v >> 5) & 0x7) == 0x7)
+               dprintk("FE%d : MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND", fe->id);
+       else
+               return 0xff;
+
+       /* revision only */
+       if ((v & 0x1f) == 0x3)
+               dprintk("FE%d : P1-D/E/F detected", fe->id);
+       else if ((v & 0x1f) == 0x1)
+               dprintk("FE%d : P1C detected", fe->id);
+       else if ((v & 0x1f) == 0x0) {
+#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
+               dprintk("FE%d : P1-A/B detected: using previous driver - support will be removed soon", fe->id);
+               dib0090_p1b_register(fe);
+#else
+               dprintk("FE%d : P1-A/B detected: driver is deactivated - not available", fe->id);
+               return 0xff;
+#endif
+       }
+
+       return v;
+}
+
+static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+
+       HARD_RESET(state);
+
+       dib0090_write_reg(state, 0x24, EN_PLL);
+       dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL);        /* PLL, DIG_CLK and CRYSTAL remain */
+
+       /* adcClkOutRatio=8->7, release reset */
+       dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
+       if (cfg->clkoutdrive != 0)
+               dib0090_write_reg(state, 0x23,
+                                 (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (cfg->clkoutdrive << 5) | (cfg->
+                                                                                                                                          clkouttobamse
+                                                                                                                                          << 4) | (0
+                                                                                                                                                   <<
+                                                                                                                                                   2)
+                                 | (0));
+       else
+               dib0090_write_reg(state, 0x23,
+                                 (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (7 << 5) | (cfg->
+                                                                                                                           clkouttobamse << 4) | (0
+                                                                                                                                                  <<
+                                                                                                                                                  2)
+                                 | (0));
+
+       /* enable pll, de-activate reset, ratio: 2/1 = 60MHz */
+       dib0090_write_reg(state, 0x21,
+                         (cfg->io.pll_bypass << 15) | (1 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv));
+
+}
+
+static int dib0090_wakeup(struct dvb_frontend *fe)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       if (state->config->sleep)
+               state->config->sleep(fe, 0);
+       return 0;
+}
+
+static int dib0090_sleep(struct dvb_frontend *fe)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       if (state->config->sleep)
+               state->config->sleep(fe, 1);
+       return 0;
+}
+
+extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       if (fast)
+               dib0090_write_reg(state, 0x04, 0);      //1kHz
+       else
+               dib0090_write_reg(state, 0x04, 1);      //almost frozen
+}
+
+EXPORT_SYMBOL(dib0090_dcc_freq);
+static const u16 rf_ramp_pwm_cband[] = {
+       0,                      /* max RF gain in 10th of dB */
+       0,                      /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
+       0,                      /* ramp_max = maximum X used on the ramp */
+       (0 << 10) | 0,          /* 0x2c, LNA 1 = 0dB */
+       (0 << 10) | 0,          /* 0x2d, LNA 1 */
+       (0 << 10) | 0,          /* 0x2e, LNA 2 = 0dB */
+       (0 << 10) | 0,          /* 0x2f, LNA 2 */
+       (0 << 10) | 0,          /* 0x30, LNA 3 = 0dB */
+       (0 << 10) | 0,          /* 0x31, LNA 3 */
+       (0 << 10) | 0,          /* GAIN_4_1, LNA 4 = 0dB */
+       (0 << 10) | 0,          /* GAIN_4_2, LNA 4 */
+};
+
+static const u16 rf_ramp_vhf[] = {
+       412,                    /* max RF gain in 10th of dB */
+       132, 307, 127,          /* LNA1,  13.2dB */
+       105, 412, 255,          /* LNA2,  10.5dB */
+       50, 50, 127,            /* LNA3,  5dB */
+       125, 175, 127,          /* LNA4,  12.5dB */
+       0, 0, 127,              /* CBAND, 0dB */
+};
+
+static const u16 rf_ramp_uhf[] = {
+       412,                    /* max RF gain in 10th of dB */
+       132, 307, 127,          /* LNA1  : total gain = 13.2dB, point on the ramp where this amp is full gain, value to write to get full gain */
+       105, 412, 255,          /* LNA2  : 10.5 dB */
+       50, 50, 127,            /* LNA3  :  5.0 dB */
+       125, 175, 127,          /* LNA4  : 12.5 dB */
+       0, 0, 127,              /* CBAND :  0.0 dB */
+};
+
+static const u16 rf_ramp_cband[] = {
+       332,                    /* max RF gain in 10th of dB */
+       132, 252, 127,          /* LNA1,  dB */
+       80, 332, 255,           /* LNA2,  dB */
+       0, 0, 127,              /* LNA3,  dB */
+       0, 0, 127,              /* LNA4,  dB */
+       120, 120, 127,          /* LT1 CBAND */
+};
+
+static const u16 rf_ramp_pwm_vhf[] = {
+       404,                    /* max RF gain in 10th of dB */
+       25,                     /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
+       1011,                   /* ramp_max = maximum X used on the ramp */
+       (6 << 10) | 417,        /* 0x2c, LNA 1 = 13.2dB */
+       (0 << 10) | 756,        /* 0x2d, LNA 1 */
+       (16 << 10) | 756,       /* 0x2e, LNA 2 = 10.5dB */
+       (0 << 10) | 1011,       /* 0x2f, LNA 2 */
+       (16 << 10) | 290,       /* 0x30, LNA 3 = 5dB */
+       (0 << 10) | 417,        /* 0x31, LNA 3 */
+       (7 << 10) | 0,          /* GAIN_4_1, LNA 4 = 12.5dB */
+       (0 << 10) | 290,        /* GAIN_4_2, LNA 4 */
+};
+
+static const u16 rf_ramp_pwm_uhf[] = {
+       404,                    /* max RF gain in 10th of dB */
+       25,                     /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
+       1011,                   /* ramp_max = maximum X used on the ramp */
+       (6 << 10) | 417,        /* 0x2c, LNA 1 = 13.2dB */
+       (0 << 10) | 756,        /* 0x2d, LNA 1 */
+       (16 << 10) | 756,       /* 0x2e, LNA 2 = 10.5dB */
+       (0 << 10) | 1011,       /* 0x2f, LNA 2 */
+       (16 << 10) | 0,         /* 0x30, LNA 3 = 5dB */
+       (0 << 10) | 127,        /* 0x31, LNA 3 */
+       (7 << 10) | 127,        /* GAIN_4_1, LNA 4 = 12.5dB */
+       (0 << 10) | 417,        /* GAIN_4_2, LNA 4 */
+};
+
+static const u16 bb_ramp_boost[] = {
+       550,                    /* max BB gain in 10th of dB */
+       260, 260, 26,           /* BB1, 26dB */
+       290, 550, 29,           /* BB2, 29dB */
+};
+
+static const u16 bb_ramp_pwm_normal[] = {
+       500,                    /* max RF gain in 10th of dB */
+       8,                      /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x34 */
+       400,
+       (2 << 9) | 0,           /* 0x35 = 21dB */
+       (0 << 9) | 168,         /* 0x36 */
+       (2 << 9) | 168,         /* 0x37 = 29dB */
+       (0 << 9) | 400,         /* 0x38 */
+};
+
+struct slope {
+       int16_t range;
+       int16_t slope;
+};
+static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
+{
+       u8 i;
+       u16 rest;
+       u16 ret = 0;
+       for (i = 0; i < num; i++) {
+               if (val > slopes[i].range)
+                       rest = slopes[i].range;
+               else
+                       rest = val;
+               ret += (rest * slopes[i].slope) / slopes[i].range;
+               val -= rest;
+       }
+       return ret;
+}
+
+static const struct slope dib0090_wbd_slopes[3] = {
+       {66, 120},              /* -64,-52: offset -   65 */
+       {600, 170},             /* -52,-35: 65     -  665 */
+       {170, 250},             /* -45,-10: 665    - 835 */
+};
+
+static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd)
+{
+       wbd &= 0x3ff;
+       if (wbd < state->wbd_offset)
+               wbd = 0;
+       else
+               wbd -= state->wbd_offset;
+       /* -64dB is the floor */
+       return -640 + (s16) slopes_to_scale(dib0090_wbd_slopes, ARRAY_SIZE(dib0090_wbd_slopes), wbd);
+}
+
+static void dib0090_wbd_target(struct dib0090_state *state, u32 rf)
+{
+       u16 offset = 250;
+
+       /* TODO : DAB digital N+/-1 interferer perfs : offset = 10 */
+
+       if (state->current_band == BAND_VHF)
+               offset = 650;
+#ifndef FIRMWARE_FIREFLY
+       if (state->current_band == BAND_VHF)
+               offset = state->config->wbd_vhf_offset;
+       if (state->current_band == BAND_CBAND)
+               offset = state->config->wbd_cband_offset;
+#endif
+
+       state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset);
+       dprintk("wbd-target: %d dB", (u32) state->wbd_target);
+}
+
+static const int gain_reg_addr[4] = {
+       0x08, 0x0a, 0x0f, 0x01
+};
+
+static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force)
+{
+       u16 rf, bb, ref;
+       u16 i, v, gain_reg[4] = { 0 }, gain;
+       const u16 *g;
+
+       if (top_delta < -511)
+               top_delta = -511;
+       if (top_delta > 511)
+               top_delta = 511;
+
+       if (force) {
+               top_delta *= (1 << WBD_ALPHA);
+               gain_delta *= (1 << GAIN_ALPHA);
+       }
+
+       if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit))       /* overflow */
+               state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
+       else
+               state->rf_gain_limit += top_delta;
+
+       if (state->rf_gain_limit < 0)   /*underflow */
+               state->rf_gain_limit = 0;
+
+       /* use gain as a temporary variable and correct current_gain */
+       gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA;
+       if (gain_delta >= ((s16) gain - state->current_gain))   /* overflow */
+               state->current_gain = gain;
+       else
+               state->current_gain += gain_delta;
+       /* cannot be less than 0 (only if gain_delta is less than 0 we can have current_gain < 0) */
+       if (state->current_gain < 0)
+               state->current_gain = 0;
+
+       /* now split total gain to rf and bb gain */
+       gain = state->current_gain >> GAIN_ALPHA;
+
+       /* requested gain is bigger than rf gain limit - ACI/WBD adjustment */
+       if (gain > (state->rf_gain_limit >> WBD_ALPHA)) {
+               rf = state->rf_gain_limit >> WBD_ALPHA;
+               bb = gain - rf;
+               if (bb > state->bb_ramp[0])
+                       bb = state->bb_ramp[0];
+       } else {                /* high signal level -> all gains put on RF */
+               rf = gain;
+               bb = 0;
+       }
+
+       state->gain[0] = rf;
+       state->gain[1] = bb;
+
+       /* software ramp */
+       /* Start with RF gains */
+       g = state->rf_ramp + 1; /* point on RF LNA1 max gain */
+       ref = rf;
+       for (i = 0; i < 7; i++) {       /* Go over all amplifiers => 5RF amps + 2 BB amps = 7 amps */
+               if (g[0] == 0 || ref < (g[1] - g[0]))   /* if total gain of the current amp is null or this amp is not concerned because it starts to work from an higher gain value */
+                       v = 0;  /* force the gain to write for the current amp to be null */
+               else if (ref >= g[1])   /* Gain to set is higher than the high working point of this amp */
+                       v = g[2];       /* force this amp to be full gain */
+               else            /* compute the value to set to this amp because we are somewhere in his range */
+                       v = ((ref - (g[1] - g[0])) * g[2]) / g[0];
+
+               if (i == 0)     /* LNA 1 reg mapping */
+                       gain_reg[0] = v;
+               else if (i == 1)        /* LNA 2 reg mapping */
+                       gain_reg[0] |= v << 7;
+               else if (i == 2)        /* LNA 3 reg mapping */
+                       gain_reg[1] = v;
+               else if (i == 3)        /* LNA 4 reg mapping */
+                       gain_reg[1] |= v << 7;
+               else if (i == 4)        /* CBAND LNA reg mapping */
+                       gain_reg[2] = v | state->rf_lt_def;
+               else if (i == 5)        /* BB gain 1 reg mapping */
+                       gain_reg[3] = v << 3;
+               else if (i == 6)        /* BB gain 2 reg mapping */
+                       gain_reg[3] |= v << 8;
+
+               g += 3;         /* go to next gain bloc */
+
+               /* When RF is finished, start with BB */
+               if (i == 4) {
+                       g = state->bb_ramp + 1; /* point on BB gain 1 max gain */
+                       ref = bb;
+               }
+       }
+       gain_reg[3] |= state->bb_1_def;
+       gain_reg[3] |= ((bb % 10) * 100) / 125;
+
+#ifdef DEBUG_AGC
+       dprintk("GA CALC: DB: %3d(rf) + %3d(bb) = %3d gain_reg[0]=%04x gain_reg[1]=%04x gain_reg[2]=%04x gain_reg[0]=%04x", rf, bb, rf + bb,
+               gain_reg[0], gain_reg[1], gain_reg[2], gain_reg[3]);
+#endif
+
+       /* Write the amplifier regs */
+       for (i = 0; i < 4; i++) {
+               v = gain_reg[i];
+               if (force || state->gain_reg[i] != v) {
+                       state->gain_reg[i] = v;
+                       dib0090_write_reg(state, gain_reg_addr[i], v);
+               }
+       }
+}
+
+static void dib0090_set_boost(struct dib0090_state *state, int onoff)
+{
+       state->bb_1_def &= 0xdfff;
+       state->bb_1_def |= onoff << 13;
+}
+
+static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg)
+{
+       state->rf_ramp = cfg;
+}
+
+static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg)
+{
+       state->rf_ramp = cfg;
+
+       dib0090_write_reg(state, 0x2a, 0xffff);
+
+       dprintk("total RF gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x2a));
+
+       dib0090_write_regs(state, 0x2c, cfg + 3, 6);
+       dib0090_write_regs(state, 0x3e, cfg + 9, 2);
+}
+
+static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg)
+{
+       state->bb_ramp = cfg;
+       dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
+}
+
+static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg)
+{
+       state->bb_ramp = cfg;
+
+       dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
+
+       dib0090_write_reg(state, 0x33, 0xffff);
+       dprintk("total BB gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x33));
+       dib0090_write_regs(state, 0x35, cfg + 3, 4);
+}
+
+void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       /* reset the AGC */
+
+       if (state->config->use_pwm_agc) {
+#ifdef CONFIG_BAND_SBAND
+               if (state->current_band == BAND_SBAND) {
+                       dib0090_set_rframp_pwm(state, rf_ramp_pwm_sband);
+                       dib0090_set_bbramp_pwm(state, bb_ramp_pwm_boost);
+               } else
+#endif
+#ifdef CONFIG_BAND_CBAND
+               if (state->current_band == BAND_CBAND) {
+                       dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
+                       dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+               } else
+#endif
+#ifdef CONFIG_BAND_VHF
+               if (state->current_band == BAND_VHF) {
+                       dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
+                       dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+               } else
+#endif
+               {
+                       dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
+                       dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+               }
+
+               if (state->rf_ramp[0] != 0)
+                       dib0090_write_reg(state, 0x32, (3 << 11));
+               else
+                       dib0090_write_reg(state, 0x32, (0 << 11));
+
+               dib0090_write_reg(state, 0x39, (1 << 10));      // 0 gain by default
+       }
+}
+
+EXPORT_SYMBOL(dib0090_pwm_gain_reset);
+int dib0090_gain_control(struct dvb_frontend *fe)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       enum frontend_tune_state *tune_state = &state->tune_state;
+       int ret = 10;
+
+       u16 wbd_val = 0;
+       u8 apply_gain_immediatly = 1;
+       s16 wbd_error = 0, adc_error = 0;
+
+       if (*tune_state == CT_AGC_START) {
+               state->agc_freeze = 0;
+               dib0090_write_reg(state, 0x04, 0x0);
+
+#ifdef CONFIG_BAND_SBAND
+               if (state->current_band == BAND_SBAND) {
+                       dib0090_set_rframp(state, rf_ramp_sband);
+                       dib0090_set_bbramp(state, bb_ramp_boost);
+               } else
+#endif
+#ifdef CONFIG_BAND_VHF
+               if (state->current_band == BAND_VHF) {
+                       dib0090_set_rframp(state, rf_ramp_vhf);
+                       dib0090_set_bbramp(state, bb_ramp_boost);
+               } else
+#endif
+#ifdef CONFIG_BAND_CBAND
+               if (state->current_band == BAND_CBAND) {
+                       dib0090_set_rframp(state, rf_ramp_cband);
+                       dib0090_set_bbramp(state, bb_ramp_boost);
+               } else
+#endif
+               {
+                       dib0090_set_rframp(state, rf_ramp_uhf);
+                       dib0090_set_bbramp(state, bb_ramp_boost);
+               }
+
+               dib0090_write_reg(state, 0x32, 0);
+               dib0090_write_reg(state, 0x39, 0);
+
+               dib0090_wbd_target(state, state->current_rf);
+
+               state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
+               state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA;
+
+               *tune_state = CT_AGC_STEP_0;
+       } else if (!state->agc_freeze) {
+               s16 wbd;
+
+               int adc;
+               wbd_val = dib0090_read_reg(state, 0x1d);
+
+               /* read and calc the wbd power */
+               wbd = dib0090_wbd_to_db(state, wbd_val);
+               wbd_error = state->wbd_target - wbd;
+
+               if (*tune_state == CT_AGC_STEP_0) {
+                       if (wbd_error < 0 && state->rf_gain_limit > 0) {
+#ifdef CONFIG_BAND_CBAND
+                               /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
+                               u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
+                               if (state->current_band == BAND_CBAND && ltg2) {
+                                       ltg2 >>= 1;
+                                       state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */
+                               }
+#endif
+                       } else {
+                               state->agc_step = 0;
+                               *tune_state = CT_AGC_STEP_1;
+                       }
+               } else {
+                       /* calc the adc power */
+                       adc = state->config->get_adc_power(fe);
+                       adc = (adc * ((s32) 355774) + (((s32) 1) << 20)) >> 21; /* included in [0:-700] */
+
+                       adc_error = (s16) (((s32) ADC_TARGET) - adc);
+#ifdef CONFIG_STANDARD_DAB
+                       if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
+                               adc_error += 130;
+#endif
+#ifdef CONFIG_STANDARD_DVBT
+                       if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
+                           (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
+                               adc_error += 60;
+#endif
+#ifdef CONFIG_SYS_ISDBT
+                       if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
+                                                                                              0)
+                                                                                             &&
+                                                                                             ((state->fe->dtv_property_cache.layer[0].modulation ==
+                                                                                               QAM_64)
+                                                                                              || (state->fe->dtv_property_cache.layer[0].
+                                                                                                  modulation == QAM_16)))
+                                                                                            ||
+                                                                                            ((state->fe->dtv_property_cache.layer[1].segment_count >
+                                                                                              0)
+                                                                                             &&
+                                                                                             ((state->fe->dtv_property_cache.layer[1].modulation ==
+                                                                                               QAM_64)
+                                                                                              || (state->fe->dtv_property_cache.layer[1].
+                                                                                                  modulation == QAM_16)))
+                                                                                            ||
+                                                                                            ((state->fe->dtv_property_cache.layer[2].segment_count >
+                                                                                              0)
+                                                                                             &&
+                                                                                             ((state->fe->dtv_property_cache.layer[2].modulation ==
+                                                                                               QAM_64)
+                                                                                              || (state->fe->dtv_property_cache.layer[2].
+                                                                                                  modulation == QAM_16)))
+                           )
+                           )
+                               adc_error += 60;
+#endif
+
+                       if (*tune_state == CT_AGC_STEP_1) {     /* quickly go to the correct range of the ADC power */
+                               if (ABS(adc_error) < 50 || state->agc_step++ > 5) {
+
+#ifdef CONFIG_STANDARD_DAB
+                                       if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) {
+                                               dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63));      /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */
+                                               dib0090_write_reg(state, 0x04, 0x0);
+                                       } else
+#endif
+                                       {
+                                               dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32));
+                                               dib0090_write_reg(state, 0x04, 0x01);   /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */
+                                       }
+
+                                       *tune_state = CT_AGC_STOP;
+                               }
+                       } else {
+                               /* everything higher than or equal to CT_AGC_STOP means tracking */
+                               ret = 100;      /* 10ms interval */
+                               apply_gain_immediatly = 0;
+                       }
+               }
+#ifdef DEBUG_AGC
+               dprintk
+                   ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
+                    (u32) fe->id, (u32) * tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
+                    (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
+#endif
+       }
+
+       /* apply gain */
+       if (!state->agc_freeze)
+               dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
+       return ret;
+}
+
+EXPORT_SYMBOL(dib0090_gain_control);
+void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       if (rf)
+               *rf = state->gain[0];
+       if (bb)
+               *bb = state->gain[1];
+       if (rf_gain_limit)
+               *rf_gain_limit = state->rf_gain_limit;
+       if (rflt)
+               *rflt = (state->rf_lt_def >> 10) & 0x7;
+}
+
+EXPORT_SYMBOL(dib0090_get_current_gain);
+u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner)
+{
+       struct dib0090_state *st = tuner->tuner_priv;
+       return st->wbd_offset;
+}
+
+EXPORT_SYMBOL(dib0090_get_wbd_offset);
+static const u16 dib0090_defaults[] = {
+
+       25, 0x01,
+       0x0000,
+       0x99a0,
+       0x6008,
+       0x0000,
+       0x8acb,
+       0x0000,
+       0x0405,
+       0x0000,
+       0x0000,
+       0x0000,
+       0xb802,
+       0x0300,
+       0x2d12,
+       0xbac0,
+       0x7c00,
+       0xdbb9,
+       0x0954,
+       0x0743,
+       0x8000,
+       0x0001,
+       0x0040,
+       0x0100,
+       0x0000,
+       0xe910,
+       0x149e,
+
+       1, 0x1c,
+       0xff2d,
+
+       1, 0x39,
+       0x0000,
+
+       1, 0x1b,
+       EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL,
+       2, 0x1e,
+       0x07FF,
+       0x0007,
+
+       1, 0x24,
+       EN_UHF | EN_CRYSTAL,
+
+       2, 0x3c,
+       0x3ff,
+       0x111,
+       0
+};
+
+static int dib0090_reset(struct dvb_frontend *fe)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       u16 l, r, *n;
+
+       dib0090_reset_digital(fe, state->config);
+       state->revision = dib0090_identify(fe);
+
+       /* Revision definition */
+       if (state->revision == 0xff)
+               return -EINVAL;
+#ifdef EFUSE
+       else if ((state->revision & 0x1f) >= 3) /* Update the efuse : Only available for KROSUS > P1C */
+               dib0090_set_EFUSE(state);
+#endif
+
+#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
+       if (!(state->revision & 0x1))   /* it is P1B - reset is already done */
+               return 0;
+#endif
+
+       /* Upload the default values */
+       n = (u16 *) dib0090_defaults;
+       l = pgm_read_word(n++);
+       while (l) {
+               r = pgm_read_word(n++);
+               do {
+                       /* DEBUG_TUNER */
+                       /* dprintk("%d, %d, %d", l, r, pgm_read_word(n)); */
+                       dib0090_write_reg(state, r, pgm_read_word(n++));
+                       r++;
+               } while (--l);
+               l = pgm_read_word(n++);
+       }
+
+       /* Congigure in function of the crystal */
+       if (state->config->io.clock_khz >= 24000)
+               l = 1;
+       else
+               l = 2;
+       dib0090_write_reg(state, 0x14, l);
+       dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
+
+       state->reset = 3;       /* enable iq-offset-calibration and wbd-calibration when tuning next time */
+
+       return 0;
+}
+
+#define steps(u) (((u)>15)?((u)-16):(u))
+#define INTERN_WAIT 10
+static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state)
+{
+       int ret = INTERN_WAIT * 10;
+
+       switch (*tune_state) {
+       case CT_TUNER_STEP_2:
+               /* Turns to positive */
+               dib0090_write_reg(state, 0x1f, 0x7);
+               *tune_state = CT_TUNER_STEP_3;
+               break;
+
+       case CT_TUNER_STEP_3:
+               state->adc_diff = dib0090_read_reg(state, 0x1d);
+
+               /* Turns to negative */
+               dib0090_write_reg(state, 0x1f, 0x4);
+               *tune_state = CT_TUNER_STEP_4;
+               break;
+
+       case CT_TUNER_STEP_4:
+               state->adc_diff -= dib0090_read_reg(state, 0x1d);
+               *tune_state = CT_TUNER_STEP_5;
+               ret = 0;
+               break;
+
+       default:
+               break;
+       }
+
+       return ret;
+}
+
+struct dc_calibration {
+       uint8_t addr;
+       uint8_t offset;
+       uint8_t pga:1;
+       uint16_t bb1;
+       uint8_t i:1;
+};
+
+static const struct dc_calibration dc_table[] = {
+       /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
+       {0x06, 5, 1, (1 << 13) | (0 << 8) | (26 << 3), 1},
+       {0x07, 11, 1, (1 << 13) | (0 << 8) | (26 << 3), 0},
+       /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
+       {0x06, 0, 0, (1 << 13) | (29 << 8) | (26 << 3), 1},
+       {0x06, 10, 0, (1 << 13) | (29 << 8) | (26 << 3), 0},
+       {0},
+};
+
+static void dib0090_set_trim(struct dib0090_state *state)
+{
+       u16 *val;
+
+       if (state->dc->addr == 0x07)
+               val = &state->bb7;
+       else
+               val = &state->bb6;
+
+       *val &= ~(0x1f << state->dc->offset);
+       *val |= state->step << state->dc->offset;
+
+       dib0090_write_reg(state, state->dc->addr, *val);
+}
+
+static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
+{
+       int ret = 0;
+
+       switch (*tune_state) {
+
+       case CT_TUNER_START:
+               /* init */
+               dprintk("Internal DC calibration");
+
+               /* the LNA is off */
+               dib0090_write_reg(state, 0x24, 0x02ed);
+
+               /* force vcm2 = 0.8V */
+               state->bb6 = 0;
+               state->bb7 = 0x040d;
+
+               state->dc = dc_table;
+
+               *tune_state = CT_TUNER_STEP_0;
+
+               /* fall through */
+
+       case CT_TUNER_STEP_0:
+               dib0090_write_reg(state, 0x01, state->dc->bb1);
+               dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
+
+               state->step = 0;
+
+               state->min_adc_diff = 1023;
+
+               *tune_state = CT_TUNER_STEP_1;
+               ret = 50;
+               break;
+
+       case CT_TUNER_STEP_1:
+               dib0090_set_trim(state);
+
+               *tune_state = CT_TUNER_STEP_2;
+               break;
+
+       case CT_TUNER_STEP_2:
+       case CT_TUNER_STEP_3:
+       case CT_TUNER_STEP_4:
+               ret = dib0090_get_offset(state, tune_state);
+               break;
+
+       case CT_TUNER_STEP_5:   /* found an offset */
+               dprintk("FE%d: IQC read=%d, current=%x", state->fe->id, (u32) state->adc_diff, state->step);
+
+               /* first turn for this frequency */
+               if (state->step == 0) {
+                       if (state->dc->pga && state->adc_diff < 0)
+                               state->step = 0x10;
+                       if (state->dc->pga == 0 && state->adc_diff > 0)
+                               state->step = 0x10;
+               }
+
+               state->adc_diff = ABS(state->adc_diff);
+
+               if (state->adc_diff < state->min_adc_diff && steps(state->step) < 15) { /* stop search when the delta to 0 is increasing */
+                       state->step++;
+                       state->min_adc_diff = state->adc_diff;
+                       *tune_state = CT_TUNER_STEP_1;
+               } else {
+
+                       /* the minimum was what we have seen in the step before */
+                       state->step--;
+                       dib0090_set_trim(state);
+
+                       dprintk("FE%d: BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->fe->id, state->dc->addr, state->adc_diff,
+                               state->step);
+
+                       state->dc++;
+                       if (state->dc->addr == 0)       /* done */
+                               *tune_state = CT_TUNER_STEP_6;
+                       else
+                               *tune_state = CT_TUNER_STEP_0;
+
+               }
+               break;
+
+       case CT_TUNER_STEP_6:
+               dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
+               dib0090_write_reg(state, 0x1f, 0x7);
+               *tune_state = CT_TUNER_START;   /* reset done -> real tuning can now begin */
+               state->reset &= ~0x1;
+       default:
+               break;
+       }
+       return ret;
+}
+
+static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
+{
+       switch (*tune_state) {
+       case CT_TUNER_START:
+               /* WBD-mode=log, Bias=2, Gain=6, Testmode=1, en=1, WBDMUX=1 */
+               dib0090_write_reg(state, 0x10, 0xdb09 | (1 << 10));
+               dib0090_write_reg(state, 0x24, EN_UHF & 0x0fff);
+
+               *tune_state = CT_TUNER_STEP_0;
+               return 90;      /* wait for the WBDMUX to switch and for the ADC to sample */
+       case CT_TUNER_STEP_0:
+               state->wbd_offset = dib0090_read_reg(state, 0x1d);
+               dprintk("WBD calibration offset = %d", state->wbd_offset);
+
+               *tune_state = CT_TUNER_START;   /* reset done -> real tuning can now begin */
+               state->reset &= ~0x2;
+               break;
+       default:
+               break;
+       }
+       return 0;
+}
+
+static void dib0090_set_bandwidth(struct dib0090_state *state)
+{
+       u16 tmp;
+
+       if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000)
+               tmp = (3 << 14);
+       else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000)
+               tmp = (2 << 14);
+       else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000)
+               tmp = (1 << 14);
+       else
+               tmp = (0 << 14);
+
+       state->bb_1_def &= 0x3fff;
+       state->bb_1_def |= tmp;
+
+       dib0090_write_reg(state, 0x01, state->bb_1_def);        /* be sure that we have the right bb-filter */
+}
+
+static const struct dib0090_pll dib0090_pll_table[] = {
+#ifdef CONFIG_BAND_CBAND
+       {56000, 0, 9, 48, 6},
+       {70000, 1, 9, 48, 6},
+       {87000, 0, 8, 32, 4},
+       {105000, 1, 8, 32, 4},
+       {115000, 0, 7, 24, 6},
+       {140000, 1, 7, 24, 6},
+       {170000, 0, 6, 16, 4},
+#endif
+#ifdef CONFIG_BAND_VHF
+       {200000, 1, 6, 16, 4},
+       {230000, 0, 5, 12, 6},
+       {280000, 1, 5, 12, 6},
+       {340000, 0, 4, 8, 4},
+       {380000, 1, 4, 8, 4},
+       {450000, 0, 3, 6, 6},
+#endif
+#ifdef CONFIG_BAND_UHF
+       {580000, 1, 3, 6, 6},
+       {700000, 0, 2, 4, 4},
+       {860000, 1, 2, 4, 4},
+#endif
+#ifdef CONFIG_BAND_LBAND
+       {1800000, 1, 0, 2, 4},
+#endif
+#ifdef CONFIG_BAND_SBAND
+       {2900000, 0, 14, 1, 4},
+#endif
+};
+
+static const struct dib0090_tuning dib0090_tuning_table_fm_vhf_on_cband[] = {
+
+#ifdef CONFIG_BAND_CBAND
+       {184000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
+       {227000, 4, 3, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
+       {380000, 4, 7, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
+#endif
+#ifdef CONFIG_BAND_UHF
+       {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+#endif
+#ifdef CONFIG_BAND_LBAND
+       {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+       {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+       {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+#endif
+#ifdef CONFIG_BAND_SBAND
+       {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
+       {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
+#endif
+};
+
+static const struct dib0090_tuning dib0090_tuning_table[] = {
+
+#ifdef CONFIG_BAND_CBAND
+       {170000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
+#endif
+#ifdef CONFIG_BAND_VHF
+       {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+       {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+       {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+#endif
+#ifdef CONFIG_BAND_UHF
+       {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+       {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+#endif
+#ifdef CONFIG_BAND_LBAND
+       {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+       {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+       {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+#endif
+#ifdef CONFIG_BAND_SBAND
+       {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
+       {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
+#endif
+};
+
+#define WBD     0x781          /* 1 1 1 1 0000 0 0 1 */
+static int dib0090_tune(struct dvb_frontend *fe)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       const struct dib0090_tuning *tune = state->current_tune_table_index;
+       const struct dib0090_pll *pll = state->current_pll_table_index;
+       enum frontend_tune_state *tune_state = &state->tune_state;
+
+       u32 rf;
+       u16 lo4 = 0xe900, lo5, lo6, Den;
+       u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
+       u16 tmp, adc;
+       int8_t step_sign;
+       int ret = 10;           /* 1ms is the default delay most of the time */
+       u8 c, i;
+
+       state->current_band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
+       rf = fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
+                                                       BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->freq_offset_khz_vhf);
+       /* in any case we first need to do a reset if needed */
+       if (state->reset & 0x1)
+               return dib0090_dc_offset_calibration(state, tune_state);
+       else if (state->reset & 0x2)
+               return dib0090_wbd_calibration(state, tune_state);
+
+    /************************* VCO ***************************/
+       /* Default values for FG                                 */
+       /* from these are needed :                               */
+       /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv             */
+
+#ifdef CONFIG_SYS_ISDBT
+       if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
+               rf += 850;
+#endif
+
+       if (state->current_rf != rf) {
+               state->tuner_is_tuned = 0;
+
+               tune = dib0090_tuning_table;
+
+               tmp = (state->revision >> 5) & 0x7;
+               if (tmp == 0x4 || tmp == 0x7) {
+                       /* CBAND tuner version for VHF */
+                       if (state->current_band == BAND_FM || state->current_band == BAND_VHF) {
+                               /* Force CBAND */
+                               state->current_band = BAND_CBAND;
+                               tune = dib0090_tuning_table_fm_vhf_on_cband;
+                       }
+               }
+
+               pll = dib0090_pll_table;
+               /* Look for the interval */
+               while (rf > tune->max_freq)
+                       tune++;
+               while (rf > pll->max_freq)
+                       pll++;
+               state->current_tune_table_index = tune;
+               state->current_pll_table_index = pll;
+       }
+
+       if (*tune_state == CT_TUNER_START) {
+
+               if (state->tuner_is_tuned == 0)
+                       state->current_rf = 0;
+
+               if (state->current_rf != rf) {
+
+                       dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
+
+                       /* external loop filter, otherwise:
+                        * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
+                        * lo6 = 0x0e34 */
+                       if (pll->vco_band)
+                               lo5 = 0x049e;
+                       else if (state->config->analog_output)
+                               lo5 = 0x041d;
+                       else
+                               lo5 = 0x041c;
+
+                       lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7);  /* bit 15 is the split to the slave, we do not do it here */
+
+                       if (!state->config->io.pll_int_loop_filt)
+                               lo6 = 0xff28;
+                       else
+                               lo6 = (state->config->io.pll_int_loop_filt << 3);
+
+                       VCOF_kHz = (pll->hfdiv * rf) * 2;
+
+                       FREF = state->config->io.clock_khz;
+
+                       FBDiv = (VCOF_kHz / pll->topresc / FREF);
+                       Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
+
+                       if (Rest < LPF)
+                               Rest = 0;
+                       else if (Rest < 2 * LPF)
+                               Rest = 2 * LPF;
+                       else if (Rest > (FREF - LPF)) {
+                               Rest = 0;
+                               FBDiv += 1;
+                       } else if (Rest > (FREF - 2 * LPF))
+                               Rest = FREF - 2 * LPF;
+                       Rest = (Rest * 6528) / (FREF / 10);
+
+                       Den = 1;
+
+                       dprintk(" *****  ******* Rest value = %d", Rest);
+
+                       if (Rest > 0) {
+                               if (state->config->analog_output)
+                                       lo6 |= (1 << 2) | 2;
+                               else
+                                       lo6 |= (1 << 2) | 1;
+                               Den = 255;
+                       }
+#ifdef CONFIG_BAND_SBAND
+                       if (state->current_band == BAND_SBAND)
+                               lo6 &= 0xfffb;
+#endif
+
+                       dib0090_write_reg(state, 0x15, (u16) FBDiv);
+
+                       dib0090_write_reg(state, 0x16, (Den << 8) | 1);
+
+                       dib0090_write_reg(state, 0x17, (u16) Rest);
+
+                       dib0090_write_reg(state, 0x19, lo5);
+
+                       dib0090_write_reg(state, 0x1c, lo6);
+
+                       lo6 = tune->tuner_enable;
+                       if (state->config->analog_output)
+                               lo6 = (lo6 & 0xff9f) | 0x2;
+
+                       dib0090_write_reg(state, 0x24, lo6 | EN_LO
+#ifdef CONFIG_DIB0090_USE_PWM_AGC
+                                         | state->config->use_pwm_agc * EN_CRYSTAL
+#endif
+                           );
+
+                       state->current_rf = rf;
+
+                       /* prepare a complete captrim */
+                       state->step = state->captrim = state->fcaptrim = 64;
+
+               } else {        /* we are already tuned to this frequency - the configuration is correct  */
+
+                       /* do a minimal captrim even if the frequency has not changed */
+                       state->step = 4;
+                       state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
+               }
+               state->adc_diff = 3000;
+
+               dib0090_write_reg(state, 0x10, 0x2B1);
+
+               dib0090_write_reg(state, 0x1e, 0x0032);
+
+               ret = 20;
+               *tune_state = CT_TUNER_STEP_1;
+       } else if (*tune_state == CT_TUNER_STEP_0) {
+               /* nothing */
+       } else if (*tune_state == CT_TUNER_STEP_1) {
+               state->step /= 2;
+               dib0090_write_reg(state, 0x18, lo4 | state->captrim);
+               *tune_state = CT_TUNER_STEP_2;
+       } else if (*tune_state == CT_TUNER_STEP_2) {
+
+               adc = dib0090_read_reg(state, 0x1d);
+               dprintk("FE %d CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) fe->id, (u32) state->captrim, (u32) adc,
+                       (u32) (adc) * (u32) 1800 / (u32) 1024);
+
+               if (adc >= 400) {
+                       adc -= 400;
+                       step_sign = -1;
+               } else {
+                       adc = 400 - adc;
+                       step_sign = 1;
+               }
+
+               if (adc < state->adc_diff) {
+                       dprintk("FE %d CAPTRIM=%d is closer to target (%d/%d)", (u32) fe->id, (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
+                       state->adc_diff = adc;
+                       state->fcaptrim = state->captrim;
+
+               }
+
+               state->captrim += step_sign * state->step;
+               if (state->step >= 1)
+                       *tune_state = CT_TUNER_STEP_1;
+               else
+                       *tune_state = CT_TUNER_STEP_3;
+
+               ret = 15;
+       } else if (*tune_state == CT_TUNER_STEP_3) {
+               /*write the final cptrim config */
+               dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
+
+#ifdef CONFIG_TUNER_DIB0090_CAPTRIM_MEMORY
+               state->memory[state->memory_index].cap = state->fcaptrim;
+#endif
+
+               *tune_state = CT_TUNER_STEP_4;
+       } else if (*tune_state == CT_TUNER_STEP_4) {
+               dib0090_write_reg(state, 0x1e, 0x07ff);
+
+               dprintk("FE %d Final Captrim: %d", (u32) fe->id, (u32) state->fcaptrim);
+               dprintk("FE %d HFDIV code: %d", (u32) fe->id, (u32) pll->hfdiv_code);
+               dprintk("FE %d VCO = %d", (u32) fe->id, (u32) pll->vco_band);
+               dprintk("FE %d VCOF in kHz: %d ((%d*%d) << 1))", (u32) fe->id, (u32) ((pll->hfdiv * rf) * 2), (u32) pll->hfdiv, (u32) rf);
+               dprintk("FE %d REFDIV: %d, FREF: %d", (u32) fe->id, (u32) 1, (u32) state->config->io.clock_khz);
+               dprintk("FE %d FBDIV: %d, Rest: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
+               dprintk("FE %d Num: %d, Den: %d, SD: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x17),
+                       (u32) (dib0090_read_reg(state, 0x16) >> 8), (u32) dib0090_read_reg(state, 0x1c) & 0x3);
+
+               c = 4;
+               i = 3;
+#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
+               if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) {
+                       c = 2;
+                       i = 2;
+               }
+#endif
+               dib0090_write_reg(state, 0x10, (c << 13) | (i << 11) | (WBD
+#ifdef CONFIG_DIB0090_USE_PWM_AGC
+                                                                       | (state->config->use_pwm_agc << 1)
+#endif
+                                 ));
+               dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | (tune->lna_bias << 0));
+               dib0090_write_reg(state, 0x0c, tune->v2i);
+               dib0090_write_reg(state, 0x0d, tune->mix);
+               dib0090_write_reg(state, 0x0e, tune->load);
+
+               *tune_state = CT_TUNER_STEP_5;
+       } else if (*tune_state == CT_TUNER_STEP_5) {
+
+               /* initialize the lt gain register */
+               state->rf_lt_def = 0x7c00;
+               dib0090_write_reg(state, 0x0f, state->rf_lt_def);
+
+               dib0090_set_bandwidth(state);
+               state->tuner_is_tuned = 1;
+               *tune_state = CT_TUNER_STOP;
+       } else
+               ret = FE_CALLBACK_TIME_NEVER;
+       return ret;
+}
+
+static int dib0090_release(struct dvb_frontend *fe)
+{
+       kfree(fe->tuner_priv);
+       fe->tuner_priv = NULL;
+       return 0;
+}
+
+enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+
+       return state->tune_state;
+}
+
+EXPORT_SYMBOL(dib0090_get_tune_state);
+
+int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+
+       state->tune_state = tune_state;
+       return 0;
+}
+
+EXPORT_SYMBOL(dib0090_set_tune_state);
+
+static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+
+       *frequency = 1000 * state->current_rf;
+       return 0;
+}
+
+static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
+{
+       struct dib0090_state *state = fe->tuner_priv;
+       uint32_t ret;
+
+       state->tune_state = CT_TUNER_START;
+
+       do {
+               ret = dib0090_tune(fe);
+               if (ret != FE_CALLBACK_TIME_NEVER)
+                       msleep(ret / 10);
+               else
+                       break;
+       } while (state->tune_state != CT_TUNER_STOP);
+
+       return 0;
+}
+
+static const struct dvb_tuner_ops dib0090_ops = {
+       .info = {
+                .name = "DiBcom DiB0090",
+                .frequency_min = 45000000,
+                .frequency_max = 860000000,
+                .frequency_step = 1000,
+                },
+       .release = dib0090_release,
+
+       .init = dib0090_wakeup,
+       .sleep = dib0090_sleep,
+       .set_params = dib0090_set_params,
+       .get_frequency = dib0090_get_frequency,
+};
+
+struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
+{
+       struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
+       if (st == NULL)
+               return NULL;
+
+       st->config = config;
+       st->i2c = i2c;
+       st->fe = fe;
+       fe->tuner_priv = st;
+
+       if (dib0090_reset(fe) != 0)
+               goto free_mem;
+
+       printk(KERN_INFO "DiB0090: successfully identified\n");
+       memcpy(&fe->ops.tuner_ops, &dib0090_ops, sizeof(struct dvb_tuner_ops));
+
+       return fe;
+ free_mem:
+       kfree(st);
+       fe->tuner_priv = NULL;
+       return NULL;
+}
+
+EXPORT_SYMBOL(dib0090_register);
+
+MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
+MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>");
+MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib0090.h b/drivers/media/dvb/frontends/dib0090.h
new file mode 100644 (file)
index 0000000..d72b7d7
--- /dev/null
@@ -0,0 +1,114 @@
+/*
+ * Linux-DVB Driver for DiBcom's DiB0090 base-band RF Tuner.
+ *
+ * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
+ *
+ * This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation, version 2.
+ */
+#ifndef DIB0090_H
+#define DIB0090_H
+
+struct dvb_frontend;
+struct i2c_adapter;
+
+#define DEFAULT_DIB0090_I2C_ADDRESS 0x60
+
+struct dib0090_io_config {
+       u32 clock_khz;
+
+       u8 pll_bypass:1;
+       u8 pll_range:1;
+       u8 pll_prediv:6;
+       u8 pll_loopdiv:6;
+
+       u8 adc_clock_ratio;     /* valid is 8, 7 ,6 */
+       u16 pll_int_loop_filt;  // internal loop filt value. If not fill in , default is 8165
+};
+
+struct dib0090_config {
+       struct dib0090_io_config io;
+       int (*reset) (struct dvb_frontend *, int);
+       int (*sleep) (struct dvb_frontend *, int);
+
+       /*  offset in kHz */
+       int freq_offset_khz_uhf;
+       int freq_offset_khz_vhf;
+
+       int (*get_adc_power) (struct dvb_frontend *);
+
+       u8 clkouttobamse:1;     /* activate or deactivate clock output */
+       u8 analog_output;
+
+       u8 i2c_address;
+       /* add drives and other things if necessary */
+       u16 wbd_vhf_offset;
+       u16 wbd_cband_offset;
+       u8 use_pwm_agc;
+       u8 clkoutdrive;
+};
+
+#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE))
+extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
+extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast);
+extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe);
+extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner);
+extern int dib0090_gain_control(struct dvb_frontend *fe);
+extern enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe);
+extern int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
+extern enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe);
+extern void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt);
+#else
+static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0090_config *config)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+       return NULL;
+}
+
+static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
+
+static inline void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
+
+static inline u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+       return 0;
+}
+
+static inline int dib0090_gain_control(struct dvb_frontend *fe)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+       return -ENODEV;
+}
+
+static inline enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+       return CT_DONE;
+}
+
+static inline int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+       return -ENODEV;
+}
+
+static inline num frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+return CT_SHUTDOWN,}
+
+static inline void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
+#endif
+
+#endif
index 898400d331a308da8965c6d0a983ae9b4417c6de..b924e7eec5ac867573c7a4f4c0b5ad944f88b5eb 100644 (file)
@@ -28,18 +28,6 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
 
 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB8000: "); printk(args); printk("\n"); } } while (0)
 
-enum frontend_tune_state {
-       CT_AGC_START = 20,
-       CT_AGC_STEP_0,
-       CT_AGC_STEP_1,
-       CT_AGC_STEP_2,
-       CT_AGC_STEP_3,
-       CT_AGC_STEP_4,
-       CT_AGC_STOP,
-
-       CT_DEMOD_START = 30,
-};
-
 #define FE_STATUS_TUNE_FAILED 0
 
 struct i2c_device {
@@ -852,6 +840,14 @@ static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
        return 0;
 }
 
+void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
+{
+       struct dib8000_state *state = fe->demodulator_priv;
+       dib8000_set_adc_state(state, DIBX000_ADC_ON);
+       dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
+}
+EXPORT_SYMBOL(dib8000_pwm_agc_reset);
+
 static int dib8000_agc_soft_split(struct dib8000_state *state)
 {
        u16 agc, split_offset;
@@ -939,6 +935,32 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
 
 }
 
+static const int32_t lut_1000ln_mant[] =
+{
+       908,7003,7090,7170,7244,7313,7377,7438,7495,7549,7600
+};
+
+int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode)
+{
+    struct dib8000_state *state = fe->demodulator_priv;
+    uint32_t ix =0, tmp_val =0, exp = 0, mant = 0;
+    int32_t val;
+
+    val = dib8000_read32(state, 384);
+    /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */
+    if(mode) {
+       tmp_val = val;
+       while(tmp_val>>=1)
+           exp++;
+       mant = (val * 1000 / (1<<exp));
+       ix = (uint8_t)((mant-1000)/100); /* index of the LUT */
+       val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */
+       val = (val*256)/1000;
+    }
+    return val;
+}
+EXPORT_SYMBOL(dib8000_get_adc_power);
+
 static void dib8000_update_timf(struct dib8000_state *state)
 {
        u32 timf = state->timf = dib8000_read32(state, 435);
@@ -1854,6 +1876,24 @@ static int dib8000_sleep(struct dvb_frontend *fe)
        }
 }
 
+enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe)
+{
+       struct dib8000_state *state = fe->demodulator_priv;
+       return state->tune_state;
+}
+EXPORT_SYMBOL(dib8000_get_tune_state);
+
+int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state)
+{
+       struct dib8000_state *state = fe->demodulator_priv;
+       state->tune_state = tune_state;
+       return 0;
+}
+EXPORT_SYMBOL(dib8000_set_tune_state);
+
+
+
+
 static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
 {
        struct dib8000_state *state = fe->demodulator_priv;
index 8c89482b738aab665a0e81c062693d8300c0e49a..de05a0ae9d986c593a8d5ddb386874017460d2ee 100644 (file)
@@ -46,6 +46,10 @@ extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
 extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value);
 extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff);
 extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
+extern int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state);
+extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe);
+extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe);
+extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
 #else
 static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
 {
@@ -59,35 +63,53 @@ static inline struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe
        return NULL;
 }
 
-int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
+static inline int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
 {
        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
        return -ENODEV;
 }
 
-int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
+static inline int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
 {
        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
        return -ENODEV;
 }
 
-int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
+static inline int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
 {
        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
        return -ENODEV;
 }
 
-int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+static inline int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
 {
        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
        return -ENODEV;
 }
 
-int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+static inline int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
 {
        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
        return -ENODEV;
 }
+static inline int dib8000_set_tune_state(struct dvb_frontend* fe, enum frontend_tune_state tune_state)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+       return -ENODEV;
+}
+static inline enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend* fe)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+    return CT_SHUTDOWN,
+}
+static inline void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
+static inline s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
+{
+       printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+}
 #endif
 
 #endif
index 4efca30d2127cbf40b1618274755413a8a210429..e6f3d73db9d33e6cac8fbf34aa969cbf24de530e 100644 (file)
@@ -6,7 +6,7 @@ static int debug;
 module_param(debug, int, 0644);
 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
 
-#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiBX000: "); printk(args); } } while (0)
+#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiBX000: "); printk(args); printk("\n"); } } while (0)
 
 static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val)
 {
@@ -25,7 +25,7 @@ static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst,
                                        enum dibx000_i2c_interface intf)
 {
        if (mst->device_rev > DIB3000MC && mst->selected_interface != intf) {
-               dprintk("selecting interface: %d\n", intf);
+               dprintk("selecting interface: %d", intf);
                mst->selected_interface = intf;
                return dibx000_write_word(mst, mst->base_reg + 4, intf);
        }
@@ -171,9 +171,18 @@ void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst)
 {
        i2c_del_adapter(&mst->gated_tuner_i2c_adap);
 }
-
 EXPORT_SYMBOL(dibx000_exit_i2c_master);
 
+
+u32 systime()
+{
+    struct timespec t;
+
+    t = current_kernel_time();
+    return (t.tv_sec * 10000) + (t.tv_nsec / 100000);
+}
+EXPORT_SYMBOL(systime);
+
 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
 MODULE_DESCRIPTION("Common function the DiBcom demodulator family");
 MODULE_LICENSE("GPL");
index 5be10eca07c025ee37e18c59cd7d30c277d7fb74..06328d8742f8eca398438d0656e4b1116bc52a91 100644 (file)
@@ -36,13 +36,17 @@ extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
 
+extern u32 systime(void);
+
 #define BAND_LBAND 0x01
 #define BAND_UHF   0x02
 #define BAND_VHF   0x04
 #define BAND_SBAND 0x08
-#define BAND_FM           0x10
+#define BAND_FM    0x10
+#define BAND_CBAND 0x20
 
-#define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 115000 ? BAND_FM : \
+#define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 170000 ? BAND_CBAND : \
+                                                                       (freq_kHz) <= 115000 ? BAND_FM : \
                                                                        (freq_kHz) <= 250000 ? BAND_VHF : \
                                                                        (freq_kHz) <= 863000 ? BAND_UHF : \
                                                                        (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
@@ -149,4 +153,67 @@ enum dibx000_adc_states {
 #define OUTMODE_MPEG2_FIFO          5
 #define OUTMODE_ANALOG_ADC          6
 
+enum frontend_tune_state {
+    CT_TUNER_START = 10,
+    CT_TUNER_STEP_0,
+    CT_TUNER_STEP_1,
+    CT_TUNER_STEP_2,
+    CT_TUNER_STEP_3,
+    CT_TUNER_STEP_4,
+    CT_TUNER_STEP_5,
+    CT_TUNER_STEP_6,
+    CT_TUNER_STEP_7,
+    CT_TUNER_STOP,
+
+    CT_AGC_START = 20,
+    CT_AGC_STEP_0,
+    CT_AGC_STEP_1,
+    CT_AGC_STEP_2,
+    CT_AGC_STEP_3,
+    CT_AGC_STEP_4,
+    CT_AGC_STOP,
+
+       CT_DEMOD_START = 30,
+    CT_DEMOD_STEP_1,
+    CT_DEMOD_STEP_2,
+    CT_DEMOD_STEP_3,
+    CT_DEMOD_STEP_4,
+    CT_DEMOD_STEP_5,
+    CT_DEMOD_STEP_6,
+    CT_DEMOD_STEP_7,
+    CT_DEMOD_STEP_8,
+    CT_DEMOD_STEP_9,
+    CT_DEMOD_STEP_10,
+    CT_DEMOD_SEARCH_NEXT = 41,
+    CT_DEMOD_STEP_LOCKED,
+    CT_DEMOD_STOP,
+
+    CT_DONE = 100,
+    CT_SHUTDOWN,
+
+};
+
+struct dvb_frontend_parametersContext {
+#define CHANNEL_STATUS_PARAMETERS_UNKNOWN   0x01
+#define CHANNEL_STATUS_PARAMETERS_SET       0x02
+    u8 status;
+    u32 tune_time_estimation[2];
+    s32 tps_available;
+    u16 tps[9];
+};
+
+#define FE_STATUS_TUNE_FAILED          0
+#define FE_STATUS_TUNE_TIMED_OUT      -1
+#define FE_STATUS_TUNE_TIME_TOO_SHORT -2
+#define FE_STATUS_TUNE_PENDING        -3
+#define FE_STATUS_STD_SUCCESS         -4
+#define FE_STATUS_FFT_SUCCESS         -5
+#define FE_STATUS_DEMOD_SUCCESS       -6
+#define FE_STATUS_LOCKED              -7
+#define FE_STATUS_DATA_LOCKED         -8
+
+#define FE_CALLBACK_TIME_NEVER 0xffffffff
+
+#define ABS(x) ((x<0)?(-x):(x))
+
 #endif