clk/samsung: exynos5433: add pclk_decon clock
authorAndrzej Hajda <a.hajda@samsung.com>
Tue, 20 Oct 2015 09:22:33 +0000 (11:22 +0200)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Wed, 3 Feb 2016 10:03:50 +0000 (11:03 +0100)
This undocumented gate clock is used by DECON IP.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5433.c
include/dt-bindings/clock/exynos5433.h

index 55300142188bc1702352c9bd21056de298d040cb..b7f1fb702e05b28ac753fa4b454c771a0ad251ae 100644 (file)
@@ -2822,6 +2822,8 @@ static struct samsung_gate_clock disp_gate_clks[] __initdata = {
                        ENABLE_PCLK_DISP, 2, 0, 0),
        GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
                        ENABLE_PCLK_DISP, 1, 0, 0),
+       GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
+                       ENABLE_PCLK_DISP, 0, 0, 0),
 
        /* ENABLE_SCLK_DISP */
        GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
index 4f0d5667ee9d5676edf48480dc9be255f0b7c711..5c2636cb957640da5ff32122e7a48f48c53e4aad 100644 (file)
 #define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY              111
 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY               112
 
-#define DISP_NR_CLK                                    113
+#define CLK_PCLK_DECON                                 113
+
+#define DISP_NR_CLK                                    114
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER                          1