ARM: v7 setup function should invalidate L1 cache
authorRussell King <rmk+kernel@arm.linux.org.uk>
Tue, 19 May 2015 16:06:44 +0000 (17:06 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 1 Jun 2015 10:30:26 +0000 (11:30 +0100)
All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU.  This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.

This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.

ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state.  Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.

Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
31 files changed:
arch/arm/mach-bcm/Makefile
arch/arm/mach-bcm/brcmstb.h [deleted file]
arch/arm/mach-bcm/headsmp-brcmstb.S [deleted file]
arch/arm/mach-bcm/platsmp-brcmstb.c
arch/arm/mach-berlin/headsmp.S
arch/arm/mach-berlin/platsmp.c
arch/arm/mach-hisi/Makefile
arch/arm/mach-hisi/core.h
arch/arm/mach-hisi/headsmp.S [deleted file]
arch/arm/mach-hisi/platsmp.c
arch/arm/mach-imx/headsmp.S
arch/arm/mach-mvebu/headsmp-a9.S
arch/arm/mach-prima2/headsmp.S
arch/arm/mach-rockchip/core.h
arch/arm/mach-rockchip/headsmp.S
arch/arm/mach-rockchip/platsmp.c
arch/arm/mach-shmobile/common.h
arch/arm/mach-shmobile/headsmp-scu.S
arch/arm/mach-shmobile/headsmp.S
arch/arm/mach-shmobile/platsmp-apmu.c
arch/arm/mach-socfpga/core.h
arch/arm/mach-socfpga/headsmp.S
arch/arm/mach-socfpga/platsmp.c
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/headsmp.S [deleted file]
arch/arm/mach-tegra/reset.c
arch/arm/mach-tegra/reset.h
arch/arm/mach-zynq/common.h
arch/arm/mach-zynq/headsmp.S
arch/arm/mach-zynq/platsmp.c
arch/arm/mm/proc-v7.S

index 4c38674c73ecb15d92702ca58b4d0f95bf2888fe..54d274da7ccba181c8ede133a6138c597ad3fa1a 100644 (file)
@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX)   := bcm63xx.o
 ifeq ($(CONFIG_ARCH_BRCMSTB),y)
 CFLAGS_platsmp-brcmstb.o       += -march=armv7-a
 obj-y                          += brcmstb.o
-obj-$(CONFIG_SMP)              += headsmp-brcmstb.o platsmp-brcmstb.o
+obj-$(CONFIG_SMP)              += platsmp-brcmstb.o
 endif
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
deleted file mode 100644 (file)
index ec0c3d1..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __BRCMSTB_H__
-#define __BRCMSTB_H__
-
-void brcmstb_secondary_startup(void);
-
-#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
deleted file mode 100644 (file)
index 199c1ea..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * SMP boot code for secondary CPUs
- * Based on arch/arm/mach-tegra/headsmp.S
- *
- * Copyright (C) 2010 NVIDIA, Inc.
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <asm/assembler.h>
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-        .section ".text.head", "ax"
-
-ENTRY(brcmstb_secondary_startup)
-        /*
-         * Ensure CPU is in a sane state by disabling all IRQs and switching
-         * into SVC mode.
-         */
-        setmode        PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
-
-        bl      v7_invalidate_l1
-        b       secondary_startup
-ENDPROC(brcmstb_secondary_startup)
index e209e6fc7cafa553fa56ec5f0f2b845d447a0ff7..44d6bddf7a4e788044da329ce79f4a66ae6b07ed 100644 (file)
@@ -30,8 +30,6 @@
 #include <asm/mach-types.h>
 #include <asm/smp_plat.h>
 
-#include "brcmstb.h"
-
 enum {
        ZONE_MAN_CLKEN_MASK             = BIT(0),
        ZONE_MAN_RESET_CNTL_MASK        = BIT(1),
@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
         * Set the reset vector to point to the secondary_startup
         * routine
         */
-       cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
+       cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
 
        /* Unhalt the cpu */
        cpu_rst_cfg_set(cpu, 0);
index 4a4c56a58ad351f03a935b7e9b9938740ff049bf..dc82a3486b05e6b208c37fe8f93707d9388b06db 100644 (file)
 #include <linux/init.h>
 #include <asm/assembler.h>
 
-ENTRY(berlin_secondary_startup)
- ARM_BE8(setend be)
-       bl      v7_invalidate_l1
-       b       secondary_startup
-ENDPROC(berlin_secondary_startup)
-
 /*
  * If the following instruction is set in the reset exception vector, CPUs
  * will fetch the value of the software reset address vector when being
index 702e7982015abcf81ba68cde339bfa2512ad8abc..34a3753e73564ed99cf92bbaee7c94ed5a869acb 100644 (file)
@@ -22,7 +22,6 @@
 #define RESET_VECT             0x00
 #define SW_RESET_ADDR          0x94
 
-extern void berlin_secondary_startup(void);
 extern u32 boot_inst;
 
 static void __iomem *cpu_ctrl;
@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
         * Write the secondary startup address into the SW reset address
         * vector. This is used by boot_inst.
         */
-       writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR);
+       writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
 
        iounmap(vectors_base);
 unmap_scu:
index 6b7b3033de0bcfa0d22b4b5be681953354fa83d1..659db1933ed3619e987dc8c017ab8ea215762eb3 100644 (file)
@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o       := -march=armv7-a
 
 obj-y  += hisilicon.o
 obj-$(CONFIG_MCPM)             += platmcpm.o
-obj-$(CONFIG_SMP)              += platsmp.o hotplug.o headsmp.o
+obj-$(CONFIG_SMP)              += platsmp.o hotplug.o
index 92a682d8e93943e3b1aa0bb813119b8451737597..c7648ef1825c70283b3a8d1e123176cb71dafd22 100644 (file)
@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
 extern int hi3xxx_cpu_kill(unsigned int cpu);
 extern void hi3xxx_set_cpu(int cpu, bool enable);
 
-extern void hisi_secondary_startup(void);
 extern struct smp_operations hix5hd2_smp_ops;
 extern void hix5hd2_set_cpu(int cpu, bool enable);
 extern void hix5hd2_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S
deleted file mode 100644 (file)
index 81e35b1..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  Copyright (c) 2014 Hisilicon Limited.
- *  Copyright (c) 2014 Linaro Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-       __CPUINIT
-
-ENTRY(hisi_secondary_startup)
-       bl      v7_invalidate_l1
-       b       secondary_startup
index 8880c8e8b296fab3b6695c9505c886843afdac94..51744127db666baee8d140876586bfd5990fb504 100644 (file)
@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        phys_addr_t jumpaddr;
 
-       jumpaddr = virt_to_phys(hisi_secondary_startup);
+       jumpaddr = virt_to_phys(secondary_startup);
        hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
        hix5hd2_set_cpu(cpu, true);
        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
        struct device_node *node;
 
 
-       jumpaddr = virt_to_phys(hisi_secondary_startup);
+       jumpaddr = virt_to_phys(secondary_startup);
        hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
 
        node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
index de5047c8a6c87ab2fc957ed09e51897780e287fc..b5e976816b63cf3cd81926dd8378036d21b2888e 100644 (file)
@@ -25,7 +25,6 @@ diag_reg_offset:
        .endm
 
 ENTRY(v7_secondary_startup)
-       bl      v7_invalidate_l1
        set_diag_reg
        b       secondary_startup
 ENDPROC(v7_secondary_startup)
index 08d5ed46b996be2d36ad44285008ab801c90b479..48e4c4b3cd1c9a52f6e5580c531088e10aac8662 100644 (file)
@@ -21,7 +21,6 @@
 
 ENTRY(mvebu_cortex_a9_secondary_startup)
 ARM_BE8(setend be)
-       bl      v7_invalidate_l1
        bl      armada_38x_scu_power_up
        b       secondary_startup
 ENDPROC(mvebu_cortex_a9_secondary_startup)
index d86fe33c5f538a206ed26421b54482d9058b1b3b..209d9fc5c16cf49909434ac243c1f794f3d22f81 100644 (file)
@@ -15,7 +15,6 @@
  * ready for them to initialise.
  */
 ENTRY(sirfsoc_secondary_startup)
-       bl v7_invalidate_l1
         mrc     p15, 0, r0, c0, c0, 5
         and     r0, r0, #15
         adr     r4, 1f
index 39bca96b555a6f08a630aefd2a7b53a941487d39..492c048813da6c96df835f91cc6ddbf98f6b517a 100644 (file)
@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline;
 extern char rockchip_secondary_trampoline_end;
 
 extern unsigned long rockchip_boot_fn;
-extern void rockchip_secondary_startup(void);
index 46c22dedf632abb7375167e93380629f3ac44acf..d69708b0728296f77a6af33744c54305d821765d 100644 (file)
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-ENTRY(rockchip_secondary_startup)
-       mrc     p15, 0, r0, c0, c0, 0   @ read main ID register
-       ldr     r1, =0x00000c09         @ Cortex-A9 primary part number
-       teq     r0, r1
-       beq     v7_invalidate_l1
-       b       secondary_startup
-ENDPROC(rockchip_secondary_startup)
-
 ENTRY(rockchip_secondary_trampoline)
        ldr     pc, 1f
 ENDPROC(rockchip_secondary_trampoline)
index 5b4ca3c3c8797d2560c4addaad6773b974ebb2d0..2e6ab67e2284497f9fc1d8fe323c2daaa4f34809 100644 (file)
@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
                 * sram_base_addr + 8: start address for pc
                 * */
                udelay(10);
-               writel(virt_to_phys(rockchip_secondary_startup),
-                       sram_base_addr + 8);
+               writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
                writel(0xDEADBEAF, sram_base_addr + 4);
                dsb_sev();
        }
@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
        }
 
        /* set the boot function for the sram code */
-       rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
+       rockchip_boot_fn = virt_to_phys(secondary_startup);
 
        /* copy the trampoline to sram, that runs during startup of the core */
        memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
index afc60bad6fd6b7d02093b6bf7d384ec4d7914cec..476092b86c6e42420e2654a8d2abe8b8aa6dcaee 100644 (file)
@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void);
 extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
                              unsigned long arg);
 extern int shmobile_smp_cpu_disable(unsigned int cpu);
-extern void shmobile_invalidate_start(void);
 extern void shmobile_boot_scu(void);
 extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
 extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
index 69df8bfac1672202073d5096631e1897857f5a5e..fa5248c52399c9b5e78e3c1cd7c167523f306424 100644 (file)
@@ -22,7 +22,7 @@
  * Boot code for secondary CPUs.
  *
  * First we turn on L1 cache coherency for our CPU. Then we jump to
- * shmobile_invalidate_start that invalidates the cache and hands over control
+ * secondary_startup that invalidates the cache and hands over control
  * to the common ARM startup code.
  */
 ENTRY(shmobile_boot_scu)
@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu)
        bic     r2, r2, r3              @ Clear bits of our CPU (Run Mode)
        str     r2, [r0, #8]            @ write back
 
-       b       shmobile_invalidate_start
+       b       secondary_startup
 ENDPROC(shmobile_boot_scu)
 
        .text
index 50c491567e11c2a43c6d86940f186299624e3f1a..330c1fc63197df89684e03578c1c0693b8e6f24f 100644 (file)
 #include <asm/assembler.h>
 #include <asm/memory.h>
 
-#ifdef CONFIG_SMP
-ENTRY(shmobile_invalidate_start)
-       bl      v7_invalidate_l1
-       b       secondary_startup
-ENDPROC(shmobile_invalidate_start)
-#endif
-
 /*
  * Reset vector for secondary CPUs.
  * This will be mapped at address 0 by SBAR register.
index f483b560b066a78d5dd99b9dd51c0591ab85cc0b..b0790fc322824431235fc65bc8a4b1790e04a78d 100644 (file)
@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        /* For this particular CPU register boot vector */
-       shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0);
+       shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
 
        return apmu_wrap(cpu, apmu_power_on);
 }
index a0f3b1cd497cc70656637c6dd2215a07942c0b1e..767c09e954a0f905f5bb2e791273f1bcc96f370f 100644 (file)
@@ -31,7 +31,6 @@
 
 #define RSTMGR_MPUMODRST_CPU1          0x2     /* CPU1 Reset */
 
-extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);
index f65ea0af4af37dbdce42f9bf1af740b4feeb9e22..5bb0164271076eb4b4d0393d0af271493464df88 100644 (file)
@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline)
 1:     .long   .
        .long   socfpga_cpu1start_addr
 ENTRY(secondary_trampoline_end)
-
-ENTRY(socfpga_secondary_startup)
-       bl      v7_invalidate_l1
-       b       secondary_startup
-ENDPROC(socfpga_secondary_startup)
index c64d89b7c0ca80c6a61f3d8e1c7439756bb83ee2..79c5336c569ff86aaa7cd7872f2447b766ce365f 100644 (file)
@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
                memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-               writel(virt_to_phys(socfpga_secondary_startup),
+               writel(virt_to_phys(secondary_startup),
                       sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
 
                flush_cache_all();
index e48a74458c258908ae7a6751ce005df21b1f624c..fffad2426ee4bc0ea1689b0de9e760db41713a0f 100644 (file)
@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC)               += pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)                += cpuidle-tegra30.o
 endif
-obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
+obj-$(CONFIG_SMP)                      += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)       += sleep-tegra30.o
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
deleted file mode 100644 (file)
index 2072e73..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-#include "sleep.h"
-
-        .section ".text.head", "ax"
-
-ENTRY(tegra_secondary_startup)
-        check_cpu_part_num 0xc09, r8, r9
-        bleq    v7_invalidate_l1
-        b       secondary_startup
-ENDPROC(tegra_secondary_startup)
index 894c5c472184f9cf9c08f34966b83ff982766939..6fd9db54887eeebd400e425a216bce2cce9399b2 100644 (file)
@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void)
        __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
                *((u32 *)cpu_possible_mask);
        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
-               virt_to_phys((void *)tegra_secondary_startup);
+               virt_to_phys((void *)secondary_startup);
 #endif
 
 #ifdef CONFIG_PM_SLEEP
index 76a93434c6ee07b8b2357761c7a18c1335e6039e..0aee0129f8d7eb8ffea3b33bc471d4ca2aa11ef2 100644 (file)
@@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
 void __tegra_cpu_reset_handler_start(void);
 void __tegra_cpu_reset_handler(void);
 void __tegra_cpu_reset_handler_end(void);
-void tegra_secondary_startup(void);
 
 #ifdef CONFIG_PM_SLEEP
 #define tegra_cpu_lp1_mask \
index 382c60e9aa1606fa980fb6c88e1aadd286e8210f..7038cae95ddcd4769e1b56e383dd270b987923e4 100644 (file)
@@ -17,8 +17,6 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
 
-void zynq_secondary_startup(void);
-
 extern int zynq_slcr_init(void);
 extern int zynq_early_slcr_init(void);
 extern void zynq_slcr_system_reset(void);
index dd8c071941e7ff3b9f991989ede3acc5aaac856b..045c72720a4d5e1c69dd22efd3fdbfdcfe811184 100644 (file)
@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
 .globl zynq_secondary_trampoline_end
 zynq_secondary_trampoline_end:
 ENDPROC(zynq_secondary_trampoline)
-
-ENTRY(zynq_secondary_startup)
-       bl      v7_invalidate_l1
-       b       secondary_startup
-ENDPROC(zynq_secondary_startup)
index 52d768ff785711a1d9d2fc384400e754ae8ddbef..f66816c4918695a6f2000d3813a870645429f7d9 100644 (file)
@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu)
 }
 EXPORT_SYMBOL(zynq_cpun_start);
 
-static int zynq_boot_secondary(unsigned int cpu,
-                                               struct task_struct *idle)
+static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-       return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu);
+       return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
 }
 
 /*
index 3d1054f11a8aea87be84819c83fe46f2a6303a58..75ae72160099a5b3b4f439f62b1f43f02e936073 100644 (file)
@@ -336,7 +336,7 @@ __v7_pj4b_setup:
 __v7_setup:
        adr     r12, __v7_setup_stack           @ the local stack
        stmia   r12, {r0-r5, r7, r9, r11, lr}
-       bl      v7_flush_dcache_louis
+       bl      v7_invalidate_l1
        ldmia   r12, {r0-r5, r7, r9, r11, lr}
 
        mrc     p15, 0, r0, c0, c0, 0           @ read main ID register