spi/rockchip: fix endian mode for 16-bit transfers

16-bit transfers must be in big endian mode on wire.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 6cdb4d81d66c87842f5ffd3a045bee3f161dd12e..9a5c51764833218b40317e04eee8d2a56980d409 100644 (file)
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -506,7 +506,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
        int rsd = 0;
 
        u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
-               | (CR0_SSD_ONE << CR0_SSD_OFFSET);
+               | (CR0_SSD_ONE << CR0_SSD_OFFSET)
+               | (CR0_EM_BIG << CR0_EM_OFFSET);
 
        cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
        cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);