ath10k: various sdio related definitions
authorErik Stromdahl <erik.stromdahl@gmail.com>
Wed, 26 Apr 2017 09:17:55 +0000 (12:17 +0300)
committerKalle Valo <kvalo@qca.qualcomm.com>
Thu, 4 May 2017 12:55:31 +0000 (15:55 +0300)
Debug masks for SDIO HIF layer.
Address definitions for SDIO/mbox based chipsets.
Augmented struct host_interest with more members.

Signed-off-by: Erik Stromdahl <erik.stromdahl@gmail.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
drivers/net/wireless/ath/ath10k/core.h
drivers/net/wireless/ath/ath10k/debug.h
drivers/net/wireless/ath/ath10k/hw.h
drivers/net/wireless/ath/ath10k/targaddrs.h

index bf091514ecc6bd220af20c68eaab00528ae2ef4c..8fc08a5043db204b722f75707c24af313e4251ea 100644 (file)
@@ -91,6 +91,7 @@ struct ath10k;
 enum ath10k_bus {
        ATH10K_BUS_PCI,
        ATH10K_BUS_AHB,
+       ATH10K_BUS_SDIO,
 };
 
 static inline const char *ath10k_bus_str(enum ath10k_bus bus)
@@ -100,6 +101,8 @@ static inline const char *ath10k_bus_str(enum ath10k_bus bus)
                return "pci";
        case ATH10K_BUS_AHB:
                return "ahb";
+       case ATH10K_BUS_SDIO:
+               return "sdio";
        }
 
        return "unknown";
index 2368f47314ae81994d337f948a685c55477c2b85..257d10985c6e21ae5a27d7408666f783576e8235 100644 (file)
@@ -38,6 +38,8 @@ enum ath10k_debug_mask {
        ATH10K_DBG_WMI_PRINT    = 0x00002000,
        ATH10K_DBG_PCI_PS       = 0x00004000,
        ATH10K_DBG_AHB          = 0x00008000,
+       ATH10K_DBG_SDIO         = 0x00010000,
+       ATH10K_DBG_SDIO_DUMP    = 0x00020000,
        ATH10K_DBG_ANY          = 0xffffffff,
 };
 
index 5b1e90bb2a4db2ddeebbd1c3383f096889e1e9a3..d34272803fd71a5db2fb77e3af074ff1d18c3c42 100644 (file)
@@ -863,6 +863,59 @@ ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw,
 #define QCA9887_EEPROM_ADDR_LO_MASK            0x00ff0000
 #define QCA9887_EEPROM_ADDR_LO_LSB             16
 
+#define MBOX_RESET_CONTROL_ADDRESS             0x00000000
+#define MBOX_HOST_INT_STATUS_ADDRESS           0x00000800
+#define MBOX_HOST_INT_STATUS_ERROR_LSB         7
+#define MBOX_HOST_INT_STATUS_ERROR_MASK                0x00000080
+#define MBOX_HOST_INT_STATUS_CPU_LSB           6
+#define MBOX_HOST_INT_STATUS_CPU_MASK          0x00000040
+#define MBOX_HOST_INT_STATUS_COUNTER_LSB       4
+#define MBOX_HOST_INT_STATUS_COUNTER_MASK      0x00000010
+#define MBOX_CPU_INT_STATUS_ADDRESS            0x00000801
+#define MBOX_ERROR_INT_STATUS_ADDRESS          0x00000802
+#define MBOX_ERROR_INT_STATUS_WAKEUP_LSB       2
+#define MBOX_ERROR_INT_STATUS_WAKEUP_MASK      0x00000004
+#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
+#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK        0x00000002
+#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB  0
+#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
+#define MBOX_COUNTER_INT_STATUS_ADDRESS                0x00000803
+#define MBOX_COUNTER_INT_STATUS_COUNTER_LSB    0
+#define MBOX_COUNTER_INT_STATUS_COUNTER_MASK   0x000000ff
+#define MBOX_RX_LOOKAHEAD_VALID_ADDRESS                0x00000805
+#define MBOX_INT_STATUS_ENABLE_ADDRESS         0x00000828
+#define MBOX_INT_STATUS_ENABLE_ERROR_LSB       7
+#define MBOX_INT_STATUS_ENABLE_ERROR_MASK      0x00000080
+#define MBOX_INT_STATUS_ENABLE_CPU_LSB         6
+#define MBOX_INT_STATUS_ENABLE_CPU_MASK                0x00000040
+#define MBOX_INT_STATUS_ENABLE_INT_LSB         5
+#define MBOX_INT_STATUS_ENABLE_INT_MASK                0x00000020
+#define MBOX_INT_STATUS_ENABLE_COUNTER_LSB     4
+#define MBOX_INT_STATUS_ENABLE_COUNTER_MASK    0x00000010
+#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB   0
+#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK  0x0000000f
+#define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS     0x00000819
+#define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB     0
+#define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK    0x000000ff
+#define MBOX_ERROR_STATUS_ENABLE_ADDRESS       0x0000081a
+#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB  1
+#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
+#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB   0
+#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK  0x00000001
+#define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b
+#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
+#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK        0x000000ff
+#define MBOX_COUNT_ADDRESS                     0x00000820
+#define MBOX_COUNT_DEC_ADDRESS                 0x00000840
+#define MBOX_WINDOW_DATA_ADDRESS               0x00000874
+#define MBOX_WINDOW_WRITE_ADDR_ADDRESS         0x00000878
+#define MBOX_WINDOW_READ_ADDR_ADDRESS          0x0000087c
+#define MBOX_CPU_DBG_SEL_ADDRESS               0x00000883
+#define MBOX_CPU_DBG_ADDRESS                   0x00000884
+#define MBOX_RTC_BASE_ADDRESS                  0x00000000
+#define MBOX_GPIO_BASE_ADDRESS                 0x00005000
+#define MBOX_MBOX_BASE_ADDRESS                 0x00008000
+
 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
 
 /* Register definitions for first generation ath10k cards. These cards include
index cbac9e4252d6fdd60c8c6750fdaeaafeaa98e9e7..8bded5da9d0d72be1fb2c93f11bbe49a59572ca3 100644 (file)
@@ -205,6 +205,24 @@ struct host_interest {
         */
        /* Bit 1 - unused */
        u32 hi_fw_swap;                                 /* 0x104 */
+
+       /* global arenas pointer address, used by host driver debug */
+       u32 hi_dynamic_mem_arenas_addr;                 /* 0x108 */
+
+       /* allocated bytes of DRAM use by allocated */
+       u32 hi_dynamic_mem_allocated;                   /* 0x10C */
+
+       /* remaining bytes of DRAM */
+       u32 hi_dynamic_mem_remaining;                   /* 0x110 */
+
+       /* memory track count, configured by host */
+       u32 hi_dynamic_mem_track_max;                   /* 0x114 */
+
+       /* minidump buffer */
+       u32 hi_minidump;                                /* 0x118 */
+
+       /* bdata's sig and key addr */
+       u32 hi_bd_sig_key;                              /* 0x11c */
 } __packed;
 
 #define HI_ITEM(item)  offsetof(struct host_interest, item)
@@ -319,6 +337,12 @@ struct host_interest {
 #define HI_ACS_FLAGS_USE_WWAN       (1 << 1)
 /* Use test VAP */
 #define HI_ACS_FLAGS_TEST_VAP       (1 << 2)
+/* SDIO/mailbox ACS flag definitions */
+#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET       (1 << 0)
+#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET    (1 << 1)
+#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE        (1 << 2)
+#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK    (1 << 16)
+#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK (1 << 17)
 
 /*
  * CONSOLE FLAGS