drm/nv04/disp: kick all private state out to own header

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index f62732dd30ad12d99157a905644de2787b8a8ce8..760af928681942f41a714da1c5c5f756722112e9 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -468,76 +468,6 @@ struct nouveau_engine {
        struct nouveau_pm_engine      pm;
 };
 
-enum nv04_fp_display_regs {
-       FP_DISPLAY_END,
-       FP_TOTAL,
-       FP_CRTC,
-       FP_SYNC_START,
-       FP_SYNC_END,
-       FP_VALID_START,
-       FP_VALID_END
-};
-
-struct nv04_crtc_reg {
-       unsigned char MiscOutReg;
-       uint8_t CRTC[0xa0];
-       uint8_t CR58[0x10];
-       uint8_t Sequencer[5];
-       uint8_t Graphics[9];
-       uint8_t Attribute[21];
-       unsigned char DAC[768];
-
-       /* PCRTC regs */
-       uint32_t fb_start;
-       uint32_t crtc_cfg;
-       uint32_t cursor_cfg;
-       uint32_t gpio_ext;
-       uint32_t crtc_830;
-       uint32_t crtc_834;
-       uint32_t crtc_850;
-       uint32_t crtc_eng_ctrl;
-
-       /* PRAMDAC regs */
-       uint32_t nv10_cursync;
-       struct nouveau_pll_vals pllvals;
-       uint32_t ramdac_gen_ctrl;
-       uint32_t ramdac_630;
-       uint32_t ramdac_634;
-       uint32_t tv_setup;
-       uint32_t tv_vtotal;
-       uint32_t tv_vskew;
-       uint32_t tv_vsync_delay;
-       uint32_t tv_htotal;
-       uint32_t tv_hskew;
-       uint32_t tv_hsync_delay;
-       uint32_t tv_hsync_delay2;
-       uint32_t fp_horiz_regs[7];
-       uint32_t fp_vert_regs[7];
-       uint32_t dither;
-       uint32_t fp_control;
-       uint32_t dither_regs[6];
-       uint32_t fp_debug_0;
-       uint32_t fp_debug_1;
-       uint32_t fp_debug_2;
-       uint32_t fp_margin_color;
-       uint32_t ramdac_8c0;
-       uint32_t ramdac_a20;
-       uint32_t ramdac_a24;
-       uint32_t ramdac_a34;
-       uint32_t ctv_regs[38];
-};
-
-struct nv04_output_reg {
-       uint32_t output;
-       int head;
-};
-
-struct nv04_mode_state {
-       struct nv04_crtc_reg crtc_reg[2];
-       uint32_t pllsel;
-       uint32_t sel_clk;
-};
-
 enum nouveau_card_type {
        NV_04      = 0x04,
        NV_10      = 0x10,
@@ -639,12 +569,6 @@ struct drm_nouveau_private {
        u8 *mxms;
        struct list_head i2c_ports;
 
-       struct nv04_mode_state mode_reg;
-       struct nv04_mode_state saved_reg;
-       uint32_t saved_vga_font[4][16384];
-       uint32_t crtc_owner;
-       uint32_t dac_users[4];
-
        struct backlight_device *backlight;
 
        struct {
@@ -997,36 +921,6 @@ extern int  nv98_ppp_create(struct drm_device *dev);
 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
                                 unsigned long arg);
 
-/* nv04_dac.c */
-extern int nv04_dac_create(struct drm_connector *, struct dcb_output *);
-extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
-extern int nv04_dac_output_offset(struct drm_encoder *encoder);
-extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
-extern bool nv04_dac_in_use(struct drm_encoder *encoder);
-
-/* nv04_dfp.c */
-extern int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
-extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
-extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
-                              int head, bool dl);
-extern void nv04_dfp_disable(struct drm_device *dev, int head);
-extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
-
-/* nv04_tv.c */
-extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
-extern int nv04_tv_create(struct drm_connector *, struct dcb_output *);
-
-/* nv17_tv.c */
-extern int nv17_tv_create(struct drm_connector *, struct dcb_output *);
-
-/* nv04_display.c */
-extern int nv04_display_early_init(struct drm_device *);
-extern void nv04_display_late_takedown(struct drm_device *);
-extern int nv04_display_create(struct drm_device *);
-extern void nv04_display_destroy(struct drm_device *);
-extern int nv04_display_init(struct drm_device *);
-extern void nv04_display_fini(struct drm_device *);
-
 /* nvd0_display.c */
 extern int nvd0_display_create(struct drm_device *);
 extern void nvd0_display_destroy(struct drm_device *);
@@ -1037,9 +931,6 @@ void nvd0_display_flip_stop(struct drm_crtc *);
 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
                           struct nouveau_channel *, u32 swap_interval);
 
-/* nv04_crtc.c */
-extern int nv04_crtc_create(struct drm_device *, int index);
-
 /* nouveau_bo.c */
 extern struct ttm_bo_driver nouveau_bo_driver;
 extern void nouveau_bo_move_init(struct nouveau_channel *);

diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index 789221d86c4a9ee803544d986d10401ecaf5f5f8..07cda5840166dba732ef8fecfdca7e605384c459 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -29,6 +29,7 @@
 
 #include "drm_encoder_slave.h"
 #include "nouveau_drv.h"
+#include "nv04_display.h"
 
 #define NV_DPMS_CLEARED 0x80
 

diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c
index fdd667b705287e269a035a04dfff073f945223bc..9cae3eb508c4a1b4e853c49f72eb8eb2c3e7f6f7 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_hw.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.c
@@ -285,17 +285,16 @@ static void nouveau_vga_font_io(struct drm_device *dev,
                                void __iomem *iovram,
                                bool save, unsigned plane)
 {
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        unsigned i;
 
        NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
        NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane);
        for (i = 0; i < 16384; i++) {
                if (save) {
-                       dev_priv->saved_vga_font[plane][i] =
+                       nv04_display(dev)->saved_vga_font[plane][i] =
                                        ioread32_native(iovram + i * 4);
                } else {
-                       iowrite32_native(dev_priv->saved_vga_font[plane][i],
+                       iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i],
                                                        iovram + i * 4);
                }
        }

diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.h b/drivers/gpu/drm/nouveau/nouveau_hw.h
index 24c4592136134af4bfc021cb9fde0afe59528bd9..feb2a2f7bd42ed372b7cd3480f843cc376885303 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_hw.h
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.h
@@ -25,6 +25,7 @@
 
 #include "drmP.h"
 #include "nouveau_drv.h"
+#include "nv04_display.h"
 
 #include <subdev/bios/pll.h>
 
@@ -437,7 +438,7 @@ nv_show_cursor(struct drm_device *dev, int head, bool show)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        uint8_t *curctl1 =
-               &dev_priv->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
+               &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
 
        if (show)
                *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);

diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index f53c6a748200ff605086e51e71b80adc1ecb1822..1cdabdc790835a94755fb8e8cf102aa1d2ae370a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -37,6 +37,7 @@
 #include "nouveau_fbcon.h"
 #include <core/ramht.h>
 #include "nouveau_pm.h"
+#include "nv04_display.h"
 #include "nv50_display.h"
 #include <engine/fifo.h>
 #include "nouveau_fence.h"

diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index 1d38968abcf1f4da1fb44067db363302f5031651..f5d17bf954ff893290b537ad7dc9b8ae7edc40e3 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -49,8 +49,8 @@ crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int in
 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
 {
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
-       struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
-       struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
+       struct drm_device *dev = crtc->dev;
+       struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
 
        regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
        if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
@@ -64,8 +64,8 @@ static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
 {
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
-       struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
-       struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
+       struct drm_device *dev = crtc->dev;
+       struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
 
        nv_crtc->sharpness = level;
        if (level < 0)  /* blur is in hw range 0x3f -> 0x20 */
@@ -105,7 +105,7 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
        struct drm_device *dev = crtc->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
-       struct nv04_mode_state *state = &dev_priv->mode_reg;
+       struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
        struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
        struct nouveau_pll_vals *pv = &regp->pllvals;
        struct nvbios_pll pll_lim;
@@ -225,9 +225,8 @@ static void
 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
 {
        struct drm_device *dev = crtc->dev;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
-       struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
+       struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
        struct drm_framebuffer *fb = crtc->fb;
 
        /* Calculate our timings */
@@ -454,8 +453,8 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
        struct drm_device *dev = crtc->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
-       struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
-       struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
+       struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
+       struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
        struct drm_encoder *encoder;
        bool lvds_output = false, tmds_output = false, tv_output = false,
                off_chip_digital = false;
@@ -533,7 +532,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
 
        /* The blob seems to take the current value from crtc 0, add 4 to that
         * and reuse the old value for crtc 1 */
-       regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
+       regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
        if (!nv_crtc->index)
                regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
 
@@ -622,7 +621,7 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
        nv_crtc_mode_set_vga(crtc, adjusted_mode);
        /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
        if (dev_priv->card_type == NV_40)
-               NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
+               NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
        nv_crtc_mode_set_regs(crtc, adjusted_mode);
        nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
        return 0;
@@ -631,10 +630,10 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
 static void nv_crtc_save(struct drm_crtc *crtc)
 {
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
-       struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
-       struct nv04_mode_state *state = &dev_priv->mode_reg;
+       struct drm_device *dev = crtc->dev;
+       struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
        struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
-       struct nv04_mode_state *saved = &dev_priv->saved_reg;
+       struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
        struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
 
        if (nv_two_heads(crtc->dev))
@@ -652,14 +651,14 @@ static void nv_crtc_save(struct drm_crtc *crtc)
 static void nv_crtc_restore(struct drm_crtc *crtc)
 {
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
-       struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
+       struct drm_device *dev = crtc->dev;
        int head = nv_crtc->index;
-       uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
+       uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
 
        if (nv_two_heads(crtc->dev))
                NVSetOwner(crtc->dev, head);
 
-       nouveau_hw_load_state(crtc->dev, head, &dev_priv->saved_reg);
+       nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
        nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
 
        nv_crtc->last_dpms = NV_DPMS_CLEARED;
@@ -692,10 +691,9 @@ static void nv_crtc_commit(struct drm_crtc *crtc)
 {
        struct drm_device *dev = crtc->dev;
        struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
-       struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
-       nouveau_hw_load_state(dev, nv_crtc->index, &dev_priv->mode_reg);
+       nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
        nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
 
 #ifdef __BIG_ENDIAN
@@ -732,18 +730,17 @@ nv_crtc_gamma_load(struct drm_crtc *crtc)
 {
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
        struct drm_device *dev = nv_crtc->base.dev;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
        int i;
 
-       rgbs = (struct rgb *)dev_priv->mode_reg.crtc_reg[nv_crtc->index].DAC;
+       rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
        for (i = 0; i < 256; i++) {
                rgbs[i].r = nv_crtc->lut.r[i] >> 8;
                rgbs[i].g = nv_crtc->lut.g[i] >> 8;
                rgbs[i].b = nv_crtc->lut.b[i] >> 8;
        }
 
-       nouveau_hw_load_state_palette(dev, nv_crtc->index, &dev_priv->mode_reg);
+       nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
 }
 
 static void
@@ -780,7 +777,7 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
        struct drm_device *dev = crtc->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
+       struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
        struct drm_framebuffer *drm_fb;
        struct nouveau_framebuffer *fb;
        int arb_burst, arb_lwm;

diff --git a/drivers/gpu/drm/nouveau/nv04_cursor.c b/drivers/gpu/drm/nouveau/nv04_cursor.c
index aaf3de3bc816c5e0d9e1d34fcd4847fa2fa3e5db..62294b8712db1dbb58566e0f0cf1a9893daa01f6 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv04_cursor.c
+++ b/drivers/gpu/drm/nouveau/nv04_cursor.c
@@ -39,7 +39,7 @@ nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
 {
        struct drm_device *dev = nv_crtc->base.dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
+       struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
        struct drm_crtc *crtc = &nv_crtc->base;
 
        regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =

diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
index a1a2c2f33d53125e9c38731b38d60ef98b7520c4..32f516ffca7529a1469d541abc398ba36b1f9074 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -407,11 +407,10 @@ static void nv04_dac_commit(struct drm_encoder *encoder)
 void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable)
 {
        struct drm_device *dev = encoder->dev;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
 
        if (nv_gf4_disp_arch(dev)) {
-               uint32_t *dac_users = &dev_priv->dac_users[ffs(dcb->or) - 1];
+               uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1];
                int dacclk_off = NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder);
                uint32_t dacclk = NVReadRAMDAC(dev, 0, dacclk_off);
 
@@ -432,11 +431,11 @@ void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable)
  * someone else. */
 bool nv04_dac_in_use(struct drm_encoder *encoder)
 {
-       struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
+       struct drm_device *dev = encoder->dev;
        struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
 
        return nv_gf4_disp_arch(encoder->dev) &&
-               (dev_priv->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
+               (nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
 }
 
 static void nv04_dac_dpms(struct drm_encoder *encoder, int mode)

diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index 823a1c5c0755f419f37f64b3991d6859f50d24ca..6d3a12fb84530a8d9826a13ee56e1d52be0ea46c 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -89,8 +89,7 @@ void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
 
 void nv04_dfp_disable(struct drm_device *dev, int head)
 {
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
+       struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
 
        if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
            FP_TG_CONTROL_ON) {
@@ -111,14 +110,13 @@ void nv04_dfp_disable(struct drm_device *dev, int head)
 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
 {
        struct drm_device *dev = encoder->dev;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct drm_crtc *crtc;
        struct nouveau_crtc *nv_crtc;
        uint32_t *fpc;
 
        if (mode == DRM_MODE_DPMS_ON) {
                nv_crtc = nouveau_crtc(encoder->crtc);
-               fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
+               fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 
                if (is_fpc_off(*fpc)) {
                        /* using saved value is ok, as (is_digital && dpms_on &&
@@ -133,7 +131,7 @@ void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
        } else {
                list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                        nv_crtc = nouveau_crtc(crtc);
-                       fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
+                       fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 
                        nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
                        if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
@@ -202,8 +200,7 @@ static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
 static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
                                     struct nouveau_encoder *nv_encoder, int head)
 {
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nv04_mode_state *state = &dev_priv->mode_reg;
+       struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
        uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
 
        if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
@@ -233,8 +230,8 @@ static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
         *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
         *      entry has the necessary info)
         */
-       if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) {
-               int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1;
+       if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
+               int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
 
                state->sel_clk &= ~0xf0;
                state->sel_clk |= (head ? 0x40 : 0x10) << shift;
@@ -246,9 +243,8 @@ static void nv04_dfp_prepare(struct drm_encoder *encoder)
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
        struct drm_encoder_helper_funcs *helper = encoder->helper_private;
        struct drm_device *dev = encoder->dev;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        int head = nouveau_crtc(encoder->crtc)->index;
-       struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
+       struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
        uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
        uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
 
@@ -284,8 +280,8 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
        struct drm_device *dev = encoder->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
-       struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
-       struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
+       struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
+       struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
        struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
        struct drm_display_mode *output_mode = &nv_encoder->mode;
@@ -459,7 +455,7 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
 
        /* update fp_control state for any changes made by scripts,
         * so correct value is written at DPMS on */
-       dev_priv->mode_reg.crtc_reg[head].fp_control =
+       nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
                NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 
        /* This could use refinement for flatpanels, but it should work this way */
@@ -511,7 +507,6 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
 {
        struct drm_device *dev = encoder->dev;
        struct drm_crtc *crtc = encoder->crtc;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
        bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
 
@@ -549,10 +544,10 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
        if (mode == DRM_MODE_DPMS_ON)
                nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
        else {
-               dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
-               dev_priv->mode_reg.sel_clk &= ~0xf0;
+               nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
+               nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
        }
-       NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
+       NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
 }
 
 static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
@@ -585,7 +580,6 @@ static void nv04_dfp_restore(struct drm_encoder *encoder)
 {
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
        struct drm_device *dev = encoder->dev;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        int head = nv_encoder->restore.head;
 
        if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
@@ -599,7 +593,7 @@ static void nv04_dfp_restore(struct drm_encoder *encoder)
 
        } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
                int clock = nouveau_hw_pllvals_to_clk
-                                       (&dev_priv->saved_reg.crtc_reg[head].pllvals);
+                                       (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
 
                run_tmds_table(dev, nv_encoder->dcb, head, clock);
        }

diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c
index 2b7d23e8f27f1bc230014a61b8b28cc008819c8f..81947ea0f82df364a854a6c73997bed604211d79 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv04_display.c
+++ b/drivers/gpu/drm/nouveau/nv04_display.c
@@ -61,10 +61,16 @@ nv04_display_create(struct drm_device *dev)
        struct drm_connector *connector, *ct;
        struct drm_encoder *encoder;
        struct drm_crtc *crtc;
+       struct nv04_display *disp;
        int i, ret;
 
        NV_DEBUG_KMS(dev, "\n");
 
+       disp = kzalloc(sizeof(*disp), GFP_KERNEL);
+       dev_priv->engine.display.priv = disp;
+       if (!disp)
+               return -ENOMEM;
+
        nouveau_hw_save_vga_fonts(dev, 1);
 
        nv04_crtc_create(dev, 0);
@@ -128,6 +134,8 @@ nv04_display_create(struct drm_device *dev)
 void
 nv04_display_destroy(struct drm_device *dev)
 {
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nv04_display *disp = nv04_display(dev);
        struct drm_encoder *encoder;
        struct drm_crtc *crtc;
 
@@ -156,6 +164,9 @@ nv04_display_destroy(struct drm_device *dev)
                crtc->funcs->restore(crtc);
 
        nouveau_hw_save_vga_fonts(dev, 0);
+
+       dev_priv->engine.display.priv = NULL;
+       kfree(disp);
 }
 
 int

diff --git a/drivers/gpu/drm/nouveau/nv04_display.h b/drivers/gpu/drm/nouveau/nv04_display.h
new file mode 100644 (file)
index 0000000..29dc4f7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv04_display.h
@@ -0,0 +1,121 @@
+#ifndef __NV04_DISPLAY_H__
+#define __NV04_DISPLAY_H__
+
+enum nv04_fp_display_regs {
+       FP_DISPLAY_END,
+       FP_TOTAL,
+       FP_CRTC,
+       FP_SYNC_START,
+       FP_SYNC_END,
+       FP_VALID_START,
+       FP_VALID_END
+};
+
+struct nv04_crtc_reg {
+       unsigned char MiscOutReg;
+       uint8_t CRTC[0xa0];
+       uint8_t CR58[0x10];
+       uint8_t Sequencer[5];
+       uint8_t Graphics[9];
+       uint8_t Attribute[21];
+       unsigned char DAC[768];
+
+       /* PCRTC regs */
+       uint32_t fb_start;
+       uint32_t crtc_cfg;
+       uint32_t cursor_cfg;
+       uint32_t gpio_ext;
+       uint32_t crtc_830;
+       uint32_t crtc_834;
+       uint32_t crtc_850;
+       uint32_t crtc_eng_ctrl;
+
+       /* PRAMDAC regs */
+       uint32_t nv10_cursync;
+       struct nouveau_pll_vals pllvals;
+       uint32_t ramdac_gen_ctrl;
+       uint32_t ramdac_630;
+       uint32_t ramdac_634;
+       uint32_t tv_setup;
+       uint32_t tv_vtotal;
+       uint32_t tv_vskew;
+       uint32_t tv_vsync_delay;
+       uint32_t tv_htotal;
+       uint32_t tv_hskew;
+       uint32_t tv_hsync_delay;
+       uint32_t tv_hsync_delay2;
+       uint32_t fp_horiz_regs[7];
+       uint32_t fp_vert_regs[7];
+       uint32_t dither;
+       uint32_t fp_control;
+       uint32_t dither_regs[6];
+       uint32_t fp_debug_0;
+       uint32_t fp_debug_1;
+       uint32_t fp_debug_2;
+       uint32_t fp_margin_color;
+       uint32_t ramdac_8c0;
+       uint32_t ramdac_a20;
+       uint32_t ramdac_a24;
+       uint32_t ramdac_a34;
+       uint32_t ctv_regs[38];
+};
+
+struct nv04_output_reg {
+       uint32_t output;
+       int head;
+};
+
+struct nv04_mode_state {
+       struct nv04_crtc_reg crtc_reg[2];
+       uint32_t pllsel;
+       uint32_t sel_clk;
+};
+
+struct nv04_display {
+       struct nv04_mode_state mode_reg;
+       struct nv04_mode_state saved_reg;
+       uint32_t saved_vga_font[4][16384];
+       uint32_t dac_users[4];
+};
+
+static inline struct nv04_display *
+nv04_display(struct drm_device *dev)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       return dev_priv->engine.display.priv;
+}
+
+/* nv04_display.c */
+int nv04_display_early_init(struct drm_device *);
+void nv04_display_late_takedown(struct drm_device *);
+int nv04_display_create(struct drm_device *);
+void nv04_display_destroy(struct drm_device *);
+int nv04_display_init(struct drm_device *);
+void nv04_display_fini(struct drm_device *);
+
+/* nv04_crtc.c */
+int nv04_crtc_create(struct drm_device *, int index);
+
+/* nv04_dac.c */
+int nv04_dac_create(struct drm_connector *, struct dcb_output *);
+uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
+int nv04_dac_output_offset(struct drm_encoder *encoder);
+void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
+bool nv04_dac_in_use(struct drm_encoder *encoder);
+
+/* nv04_dfp.c */
+int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
+int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
+void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
+                              int head, bool dl);
+void nv04_dfp_disable(struct drm_device *dev, int head);
+void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
+
+/* nv04_tv.c */
+int nv04_tv_identify(struct drm_device *dev, int i2c_index);
+int nv04_tv_create(struct drm_connector *, struct dcb_output *);
+
+/* nv17_tv.c */
+int nv17_tv_create(struct drm_connector *, struct dcb_output *);
+
+#endif

diff --git a/drivers/gpu/drm/nouveau/nv04_tv.c b/drivers/gpu/drm/nouveau/nv04_tv.c
index 5927391373e9b520073f6da168f0c490c0f202c1..5f5c25d773430bd0b81a177c10b3f246f0fb9f73 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv04_tv.c
+++ b/drivers/gpu/drm/nouveau/nv04_tv.c
@@ -65,8 +65,7 @@ static void nv04_tv_dpms(struct drm_encoder *encoder, int mode)
 {
        struct drm_device *dev = encoder->dev;
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nv04_mode_state *state = &dev_priv->mode_reg;
+       struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
        uint8_t crtc1A;
 
        NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
@@ -94,8 +93,7 @@ static void nv04_tv_dpms(struct drm_encoder *encoder, int mode)
 
 static void nv04_tv_bind(struct drm_device *dev, int head, bool bind)
 {
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nv04_crtc_reg *state = &dev_priv->mode_reg.crtc_reg[head];
+       struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
 
        state->tv_setup = 0;
 
@@ -133,9 +131,8 @@ static void nv04_tv_mode_set(struct drm_encoder *encoder,
                             struct drm_display_mode *adjusted_mode)
 {
        struct drm_device *dev = encoder->dev;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
-       struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
+       struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
 
        regp->tv_htotal = adjusted_mode->htotal;
        regp->tv_vtotal = adjusted_mode->vtotal;

diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index 54ff394e005b2b48d94d004c0e34014fad645af4..5d1f6f6de257a790960001d3469870494315d348 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -395,7 +395,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder)
        struct drm_encoder_helper_funcs *helper = encoder->helper_private;
        struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
        int head = nouveau_crtc(encoder->crtc)->index;
-       uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
+       uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
                                                        NV_CIO_CRE_LCD__INDEX];
        uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
                                        nv04_dac_output_offset(encoder);
@@ -456,7 +456,7 @@ static void nv17_tv_mode_set(struct drm_encoder *encoder,
        struct drm_device *dev = encoder->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        int head = nouveau_crtc(encoder->crtc)->index;
-       struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
+       struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
        struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
        struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
        int i;

diff --git a/drivers/gpu/drm/nouveau/nv17_tv_modes.c b/drivers/gpu/drm/nouveau/nv17_tv_modes.c
index 4d1d29f60307da70e10992e8a9e8e41faba107f2..381d388def3a11cba5e99b31ffde13e9bc214603 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv17_tv_modes.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv_modes.c
@@ -543,10 +543,9 @@ void nv17_tv_update_rescaler(struct drm_encoder *encoder)
 void nv17_ctv_update_rescaler(struct drm_encoder *encoder)
 {
        struct drm_device *dev = encoder->dev;
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
        int head = nouveau_crtc(encoder->crtc)->index;
-       struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
+       struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
        struct drm_display_mode *crtc_mode = &encoder->crtc->mode;
        struct drm_display_mode *output_mode =
                &get_tv_norm(encoder)->ctv_enc_mode.mode;