drm/radeon: use common next_reloc function

This patch eliminates ASIC-specific ***_cs_packet_next_reloc
functions and hooks up the new common function.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 02aeb7fc3778907e8628ab8c85af12d0d93e6e9a..211b509561534e43cfd4f16a37d8c00442e164ee 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -36,9 +36,6 @@
 
 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
                           struct radeon_cs_reloc **cs_reloc);
-static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
-                                         struct radeon_cs_reloc **cs_reloc);
-
 struct evergreen_cs_track {
        u32                     group_size;
        u32                     nbanks;
@@ -1008,52 +1005,6 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
        return 0;
 }
 
-/**
- * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
- * @parser:            parser structure holding parsing context.
- * @data:              pointer to relocation data
- * @offset_start:      starting offset
- * @offset_mask:       offset mask (to align start offset on)
- * @reloc:             reloc informations
- *
- * Check next packet is relocation packet3, do bo validation and compute
- * GPU offset using the provided start.
- **/
-static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
-                                         struct radeon_cs_reloc **cs_reloc)
-{
-       struct radeon_cs_chunk *relocs_chunk;
-       struct radeon_cs_packet p3reloc;
-       unsigned idx;
-       int r;
-
-       if (p->chunk_relocs_idx == -1) {
-               DRM_ERROR("No relocation chunk !\n");
-               return -EINVAL;
-       }
-       *cs_reloc = NULL;
-       relocs_chunk = &p->chunks[p->chunk_relocs_idx];
-       r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
-       if (r) {
-               return r;
-       }
-       p->idx += p3reloc.count + 2;
-       if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
-               DRM_ERROR("No packet3 for relocation for packet at %d.\n",
-                         p3reloc.idx);
-               return -EINVAL;
-       }
-       idx = radeon_get_ib_value(p, p3reloc.idx + 1);
-       if (idx >= relocs_chunk->length_dw) {
-               DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
-                         idx, relocs_chunk->length_dw);
-               return -EINVAL;
-       }
-       /* FIXME: we assume reloc size is 4 dwords */
-       *cs_reloc = p->relocs_ptr[(idx / 4)];
-       return 0;
-}
-
 /**
  * evergreen_cs_packet_parse_vline() - parse userspace VLINE packet
  * @parser:            parser structure holding parsing context.
@@ -1205,7 +1156,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case SQ_LSTMP_RING_BASE:
        case SQ_PSTMP_RING_BASE:
        case SQ_VSTMP_RING_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1234,7 +1185,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case DB_Z_INFO:
                track->db_z_info = radeon_get_ib_value(p, idx);
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                                "0x%04X\n", reg);
@@ -1276,7 +1227,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->db_dirty = true;
                break;
        case DB_Z_READ_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1288,7 +1239,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->db_dirty = true;
                break;
        case DB_Z_WRITE_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1300,7 +1251,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->db_dirty = true;
                break;
        case DB_STENCIL_READ_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1312,7 +1263,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->db_dirty = true;
                break;
        case DB_STENCIL_WRITE_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1335,7 +1286,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case VGT_STRMOUT_BUFFER_BASE_1:
        case VGT_STRMOUT_BUFFER_BASE_2:
        case VGT_STRMOUT_BUFFER_BASE_3:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1357,7 +1308,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->streamout_dirty = true;
                break;
        case CP_COHER_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
                                        "0x%04X\n", reg);
@@ -1421,7 +1372,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                tmp = (reg - CB_COLOR0_INFO) / 0x3c;
                track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                                "0x%04X\n", reg);
@@ -1439,7 +1390,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
                track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                                "0x%04X\n", reg);
@@ -1500,7 +1451,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case CB_COLOR5_ATTRIB:
        case CB_COLOR6_ATTRIB:
        case CB_COLOR7_ATTRIB:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1528,7 +1479,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case CB_COLOR9_ATTRIB:
        case CB_COLOR10_ATTRIB:
        case CB_COLOR11_ATTRIB:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1561,7 +1512,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case CB_COLOR6_FMASK:
        case CB_COLOR7_FMASK:
                tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                        return -EINVAL;
@@ -1578,7 +1529,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case CB_COLOR6_CMASK:
        case CB_COLOR7_CMASK:
                tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                        return -EINVAL;
@@ -1616,7 +1567,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case CB_COLOR5_BASE:
        case CB_COLOR6_BASE:
        case CB_COLOR7_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1632,7 +1583,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case CB_COLOR9_BASE:
        case CB_COLOR10_BASE:
        case CB_COLOR11_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1645,7 +1596,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->cb_dirty = true;
                break;
        case DB_HTILE_DATA_BASE:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1763,7 +1714,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case SQ_ALU_CONST_CACHE_LS_13:
        case SQ_ALU_CONST_CACHE_LS_14:
        case SQ_ALU_CONST_CACHE_LS_15:
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1777,7 +1728,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                 "0x%04X\n", reg);
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONFIG_REG "
                                        "0x%04X\n", reg);
@@ -1791,7 +1742,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                                 "0x%04X\n", reg);
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1876,7 +1827,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("bad SET PREDICATION\n");
                        return -EINVAL;
@@ -1922,7 +1873,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad INDEX_BASE\n");
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("bad INDEX_BASE\n");
                        return -EINVAL;
@@ -1949,7 +1900,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad DRAW_INDEX\n");
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("bad DRAW_INDEX\n");
                        return -EINVAL;
@@ -1977,7 +1928,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad DRAW_INDEX_2\n");
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("bad DRAW_INDEX_2\n");
                        return -EINVAL;
@@ -2068,7 +2019,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad DISPATCH_INDIRECT\n");
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("bad DISPATCH_INDIRECT\n");
                        return -EINVAL;
@@ -2089,7 +2040,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                if (idx_value & 0x10) {
                        uint64_t offset;
 
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("bad WAIT_REG_MEM\n");
                                return -EINVAL;
@@ -2143,7 +2094,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        }
                        /* src address space is memory */
                        if (((info & 0x60000000) >> 29) == 0) {
-                               r = evergreen_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                                if (r) {
                                        DRM_ERROR("bad CP DMA SRC\n");
                                        return -EINVAL;
@@ -2181,7 +2132,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                return -EINVAL;
                        }
                        if (((info & 0x00300000) >> 20) == 0) {
-                               r = evergreen_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                                if (r) {
                                        DRM_ERROR("bad CP DMA DST\n");
                                        return -EINVAL;
@@ -2215,7 +2166,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                /* 0xffffffff/0x0 is flush all cache flag */
                if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
                    radeon_get_ib_value(p, idx + 2) != 0) {
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("bad SURFACE_SYNC\n");
                                return -EINVAL;
@@ -2231,7 +2182,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                if (pkt->count) {
                        uint64_t offset;
 
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("bad EVENT_WRITE\n");
                                return -EINVAL;
@@ -2252,7 +2203,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad EVENT_WRITE_EOP\n");
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("bad EVENT_WRITE_EOP\n");
                        return -EINVAL;
@@ -2274,7 +2225,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad EVENT_WRITE_EOS\n");
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("bad EVENT_WRITE_EOS\n");
                        return -EINVAL;
@@ -2341,7 +2292,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
                        case SQ_TEX_VTX_VALID_TEXTURE:
                                /* tex base */
-                               r = evergreen_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                                if (r) {
                                        DRM_ERROR("bad SET_RESOURCE (tex)\n");
                                        return -EINVAL;
@@ -2378,7 +2329,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                        moffset = 0;
                                        mipmap = NULL;
                                } else {
-                                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                                        if (r) {
                                                DRM_ERROR("bad SET_RESOURCE (tex)\n");
                                                return -EINVAL;
@@ -2397,7 +2348,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        {
                                uint64_t offset64;
                                /* vtx base */
-                               r = evergreen_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                                if (r) {
                                        DRM_ERROR("bad SET_RESOURCE (vtx)\n");
                                        return -EINVAL;
@@ -2479,7 +2430,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                /* Updating memory at DST_ADDRESS. */
                if (idx_value & 0x1) {
                        u64 offset;
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
                                return -EINVAL;
@@ -2498,7 +2449,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                /* Reading data from SRC_ADDRESS. */
                if (((idx_value >> 1) & 0x3) == 2) {
                        u64 offset;
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
                                return -EINVAL;
@@ -2523,7 +2474,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad MEM_WRITE (invalid count)\n");
                        return -EINVAL;
                }
-               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
                        return -EINVAL;
@@ -2552,7 +2503,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                if (idx_value & 0x1) {
                        u64 offset;
                        /* SRC is memory. */
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("bad COPY_DW (missing src reloc)\n");
                                return -EINVAL;
@@ -2576,7 +2527,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                if (idx_value & 0x2) {
                        u64 offset;
                        /* DST is memory. */
-                       r = evergreen_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
                                return -EINVAL;

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index cf7e35903eae95c1e4390bc8a2289c1183c3a53a..846960764a05e044b34585cc3aafcf6f944a8319 100644 (file)
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1215,7 +1215,7 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
        struct radeon_cs_reloc *reloc;
        u32 value;
 
-       r = r100_cs_packet_next_reloc(p, &reloc);
+       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
        if (r) {
                DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                          idx, reg);
@@ -1268,7 +1268,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
        }
        track->num_arrays = c;
        for (i = 0; i < (c - 1); i+=2, idx+=3) {
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for packet3 %d\n",
                                  pkt->opcode);
@@ -1281,7 +1281,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
                track->arrays[i + 0].esize = idx_value >> 8;
                track->arrays[i + 0].robj = reloc->robj;
                track->arrays[i + 0].esize &= 0x7F;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for packet3 %d\n",
                                  pkt->opcode);
@@ -1294,7 +1294,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
                track->arrays[i + 1].esize &= 0x7F;
        }
        if (c & 1) {
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for packet3 %d\n",
                                          pkt->opcode);
@@ -1445,54 +1445,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
        return 0;
 }
 
-/**
- * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
- * @parser:            parser structure holding parsing context.
- * @data:              pointer to relocation data
- * @offset_start:      starting offset
- * @offset_mask:       offset mask (to align start offset on)
- * @reloc:             reloc informations
- *
- * Check next packet is relocation packet3, do bo validation and compute
- * GPU offset using the provided start.
- **/
-int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
-                             struct radeon_cs_reloc **cs_reloc)
-{
-       struct radeon_cs_chunk *relocs_chunk;
-       struct radeon_cs_packet p3reloc;
-       unsigned idx;
-       int r;
-
-       if (p->chunk_relocs_idx == -1) {
-               DRM_ERROR("No relocation chunk !\n");
-               return -EINVAL;
-       }
-       *cs_reloc = NULL;
-       relocs_chunk = &p->chunks[p->chunk_relocs_idx];
-       r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
-       if (r) {
-               return r;
-       }
-       p->idx += p3reloc.count + 2;
-       if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
-               DRM_ERROR("No packet3 for relocation for packet at %d.\n",
-                         p3reloc.idx);
-               radeon_cs_dump_packet(p, &p3reloc);
-               return -EINVAL;
-       }
-       idx = radeon_get_ib_value(p, p3reloc.idx + 1);
-       if (idx >= relocs_chunk->length_dw) {
-               DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
-                         idx, relocs_chunk->length_dw);
-               radeon_cs_dump_packet(p, &p3reloc);
-               return -EINVAL;
-       }
-       /* FIXME: we assume reloc size is 4 dwords */
-       *cs_reloc = p->relocs_ptr[(idx / 4)];
-       return 0;
-}
-
 static int r100_get_vtx_size(uint32_t vtx_fmt)
 {
        int vtx_size;
@@ -1583,7 +1535,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                break;
        case RADEON_RB3D_DEPTHOFFSET:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1596,7 +1548,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                break;
        case RADEON_RB3D_COLOROFFSET:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1612,7 +1564,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
        case RADEON_PP_TXOFFSET_1:
        case RADEON_PP_TXOFFSET_2:
                i = (reg - RADEON_PP_TXOFFSET_0) / 24;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1639,7 +1591,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
        case RADEON_PP_CUBIC_OFFSET_T0_3:
        case RADEON_PP_CUBIC_OFFSET_T0_4:
                i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1657,7 +1609,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
        case RADEON_PP_CUBIC_OFFSET_T1_3:
        case RADEON_PP_CUBIC_OFFSET_T1_4:
                i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1675,7 +1627,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
        case RADEON_PP_CUBIC_OFFSET_T2_3:
        case RADEON_PP_CUBIC_OFFSET_T2_4:
                i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1693,7 +1645,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                track->zb_dirty = true;
                break;
        case RADEON_RB3D_COLORPITCH:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1764,7 +1716,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                track->zb_dirty = true;
                break;
        case RADEON_RB3D_ZPASS_ADDR:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1925,7 +1877,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
                        return r;
                break;
        case PACKET3_INDX_BUFFER:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
                        radeon_cs_dump_packet(p, pkt);
@@ -1939,7 +1891,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
                break;
        case 0x23:
                /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
                        radeon_cs_dump_packet(p, pkt);

diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index c81b174aaf050a3550bf4564fb07eeec365f4f7f..eb40888bdfcc1e563232e51ddc6641052c9b15d7 100644 (file)
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -81,8 +81,6 @@ struct r100_cs_track {
 
 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
-int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
-                             struct radeon_cs_reloc **cs_reloc);
 
 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
 

diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 07ea6f4a990312a3326829dcd832cb2e55e4e26c..b3807edb19365e79e61bf392a66c22156803859e 100644 (file)
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -175,7 +175,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                        return r;
                break;
        case RADEON_RB3D_DEPTHOFFSET:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -188,7 +188,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                break;
        case RADEON_RB3D_COLOROFFSET:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -207,7 +207,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
        case R200_PP_TXOFFSET_4:
        case R200_PP_TXOFFSET_5:
                i = (reg - R200_PP_TXOFFSET_0) / 24;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -260,7 +260,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
        case R200_PP_CUBIC_OFFSET_F5_5:
                i = (reg - R200_PP_TXOFFSET_0) / 24;
                face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -278,7 +278,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                track->zb_dirty = true;
                break;
        case RADEON_RB3D_COLORPITCH:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -355,7 +355,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                track->zb_dirty = true;
                break;
        case RADEON_RB3D_ZPASS_ADDR:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 47bfca14cec898ae2b9e2d6a024289ed944e4213..98f723c7ef667beb0ed441d5e6ac440bbeeb68fd 100644 (file)
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -630,7 +630,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
        case R300_RB3D_COLOROFFSET2:
        case R300_RB3D_COLOROFFSET3:
                i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                        idx, reg);
@@ -643,7 +643,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                break;
        case R300_ZB_DEPTHOFFSET:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                        idx, reg);
@@ -672,7 +672,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
        case R300_TX_OFFSET_0+56:
        case R300_TX_OFFSET_0+60:
                i = (reg - R300_TX_OFFSET_0) >> 2;
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                        idx, reg);
@@ -745,7 +745,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                /* RB3D_COLORPITCH2 */
                /* RB3D_COLORPITCH3 */
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       r = r100_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                          idx, reg);
@@ -830,7 +830,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
        case 0x4F24:
                /* ZB_DEPTHPITCH */
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       r = r100_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                        if (r) {
                                DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                          idx, reg);
@@ -1045,7 +1045,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                track->tex_dirty = true;
                break;
        case R300_ZB_ZPASS_ADDR:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                        idx, reg);
@@ -1087,7 +1087,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                track->cb_dirty = true;
                break;
        case R300_RB3D_AARESOLVE_OFFSET:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
                                  idx, reg);
@@ -1156,7 +1156,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
                        return r;
                break;
        case PACKET3_INDX_BUFFER:
-               r = r100_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, 0);
                if (r) {
                        DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
                        radeon_cs_dump_packet(p, pkt);

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 9d833728ed005be06f5e8fc4464f0b56098bcc50..f8fe50cb472617b0c1c30d57857014a6f142c446 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -31,12 +31,7 @@
 #include "r600d.h"
 #include "r600_reg_safe.h"
 
-static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
-                                       struct radeon_cs_reloc **cs_reloc);
-static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
-                                       struct radeon_cs_reloc **cs_reloc);
-typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
-static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
+static int r600_nomm;
 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
 
 
@@ -783,99 +778,6 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
        return 0;
 }
 
-/**
- * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
- * @parser:            parser structure holding parsing context.
- * @data:              pointer to relocation data
- * @offset_start:      starting offset
- * @offset_mask:       offset mask (to align start offset on)
- * @reloc:             reloc informations
- *
- * Check next packet is relocation packet3, do bo validation and compute
- * GPU offset using the provided start.
- **/
-static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
-                                       struct radeon_cs_reloc **cs_reloc)
-{
-       struct radeon_cs_chunk *relocs_chunk;
-       struct radeon_cs_packet p3reloc;
-       unsigned idx;
-       int r;
-
-       if (p->chunk_relocs_idx == -1) {
-               DRM_ERROR("No relocation chunk !\n");
-               return -EINVAL;
-       }
-       *cs_reloc = NULL;
-       relocs_chunk = &p->chunks[p->chunk_relocs_idx];
-       r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
-       if (r) {
-               return r;
-       }
-       p->idx += p3reloc.count + 2;
-       if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
-               DRM_ERROR("No packet3 for relocation for packet at %d.\n",
-                         p3reloc.idx);
-               return -EINVAL;
-       }
-       idx = radeon_get_ib_value(p, p3reloc.idx + 1);
-       if (idx >= relocs_chunk->length_dw) {
-               DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
-                         idx, relocs_chunk->length_dw);
-               return -EINVAL;
-       }
-       /* FIXME: we assume reloc size is 4 dwords */
-       *cs_reloc = p->relocs_ptr[(idx / 4)];
-       return 0;
-}
-
-/**
- * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
- * @parser:            parser structure holding parsing context.
- * @data:              pointer to relocation data
- * @offset_start:      starting offset
- * @offset_mask:       offset mask (to align start offset on)
- * @reloc:             reloc informations
- *
- * Check next packet is relocation packet3, do bo validation and compute
- * GPU offset using the provided start.
- **/
-static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
-                                       struct radeon_cs_reloc **cs_reloc)
-{
-       struct radeon_cs_chunk *relocs_chunk;
-       struct radeon_cs_packet p3reloc;
-       unsigned idx;
-       int r;
-
-       if (p->chunk_relocs_idx == -1) {
-               DRM_ERROR("No relocation chunk !\n");
-               return -EINVAL;
-       }
-       *cs_reloc = NULL;
-       relocs_chunk = &p->chunks[p->chunk_relocs_idx];
-       r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
-       if (r) {
-               return r;
-       }
-       p->idx += p3reloc.count + 2;
-       if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
-               DRM_ERROR("No packet3 for relocation for packet at %d.\n",
-                         p3reloc.idx);
-               return -EINVAL;
-       }
-       idx = radeon_get_ib_value(p, p3reloc.idx + 1);
-       if (idx >= relocs_chunk->length_dw) {
-               DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
-                         idx, relocs_chunk->length_dw);
-               return -EINVAL;
-       }
-       *cs_reloc = p->relocs;
-       (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
-       (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
-       return 0;
-}
-
 /**
  * r600_cs_packet_parse_vline() - parse userspace VLINE packet
  * @parser:            parser structure holding parsing context.
@@ -1115,7 +1017,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case R_028010_DB_DEPTH_INFO:
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
                    radeon_cs_packet_next_is_pkt3_nop(p)) {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                         "0x%04X\n", reg);
@@ -1157,7 +1059,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case VGT_STRMOUT_BUFFER_BASE_1:
        case VGT_STRMOUT_BUFFER_BASE_2:
        case VGT_STRMOUT_BUFFER_BASE_3:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1180,7 +1082,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->streamout_dirty = true;
                break;
        case CP_COHER_BASE:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
                                        "0x%04X\n", reg);
@@ -1216,7 +1118,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case R_0280BC_CB_COLOR7_INFO:
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
                     radeon_cs_packet_next_is_pkt3_nop(p)) {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                                return -EINVAL;
@@ -1288,7 +1190,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
                        ib[idx] = track->cb_color_base_last[tmp];
                } else {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                                return -EINVAL;
@@ -1319,7 +1221,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                        track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
                        ib[idx] = track->cb_color_base_last[tmp];
                } else {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                                return -EINVAL;
@@ -1354,7 +1256,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case CB_COLOR5_BASE:
        case CB_COLOR6_BASE:
        case CB_COLOR7_BASE:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1369,7 +1271,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->cb_dirty = true;
                break;
        case DB_DEPTH_BASE:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1382,7 +1284,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                track->db_dirty = true;
                break;
        case DB_HTILE_DATA_BASE:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1452,7 +1354,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        case SQ_ALU_CONST_CACHE_VS_13:
        case SQ_ALU_CONST_CACHE_VS_14:
        case SQ_ALU_CONST_CACHE_VS_15:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1461,7 +1363,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                break;
        case SX_MEMORY_EXPORT_BASE:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONFIG_REG "
                                        "0x%04X\n", reg);
@@ -1747,7 +1649,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        DRM_ERROR("bad SET PREDICATION\n");
                        return -EINVAL;
@@ -1788,7 +1690,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad DRAW_INDEX\n");
                        return -EINVAL;
                }
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        DRM_ERROR("bad DRAW_INDEX\n");
                        return -EINVAL;
@@ -1840,7 +1742,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                if (idx_value & 0x10) {
                        uint64_t offset;
 
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad WAIT_REG_MEM\n");
                                return -EINVAL;
@@ -1877,7 +1779,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                return -EINVAL;
                        }
                        /* src address space is memory */
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad CP DMA SRC\n");
                                return -EINVAL;
@@ -1907,7 +1809,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                DRM_ERROR("CP DMA DAIC only supported for registers\n");
                                return -EINVAL;
                        }
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad CP DMA DST\n");
                                return -EINVAL;
@@ -1937,7 +1839,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                /* 0xffffffff/0x0 is flush all cache flag */
                if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
                    radeon_get_ib_value(p, idx + 2) != 0) {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad SURFACE_SYNC\n");
                                return -EINVAL;
@@ -1953,7 +1855,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                if (pkt->count) {
                        uint64_t offset;
 
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad EVENT_WRITE\n");
                                return -EINVAL;
@@ -1974,7 +1876,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad EVENT_WRITE_EOP\n");
                        return -EINVAL;
                }
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        DRM_ERROR("bad EVENT_WRITE\n");
                        return -EINVAL;
@@ -2040,7 +1942,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
                        case SQ_TEX_VTX_VALID_TEXTURE:
                                /* tex base */
-                               r = r600_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                                if (r) {
                                        DRM_ERROR("bad SET_RESOURCE\n");
                                        return -EINVAL;
@@ -2054,7 +1956,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                }
                                texture = reloc->robj;
                                /* tex mip base */
-                               r = r600_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                                if (r) {
                                        DRM_ERROR("bad SET_RESOURCE\n");
                                        return -EINVAL;
@@ -2075,7 +1977,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        {
                                uint64_t offset64;
                                /* vtx base */
-                               r = r600_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                                if (r) {
                                        DRM_ERROR("bad SET_RESOURCE\n");
                                        return -EINVAL;
@@ -2176,7 +2078,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                {
                        u64 offset;
 
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
                                return -EINVAL;
@@ -2220,7 +2122,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                /* Updating memory at DST_ADDRESS. */
                if (idx_value & 0x1) {
                        u64 offset;
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
                                return -EINVAL;
@@ -2239,7 +2141,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                /* Reading data from SRC_ADDRESS. */
                if (((idx_value >> 1) & 0x3) == 2) {
                        u64 offset;
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
                                return -EINVAL;
@@ -2264,7 +2166,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        DRM_ERROR("bad MEM_WRITE (invalid count)\n");
                        return -EINVAL;
                }
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
                        return -EINVAL;
@@ -2293,7 +2195,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                if (idx_value & 0x1) {
                        u64 offset;
                        /* SRC is memory. */
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad COPY_DW (missing src reloc)\n");
                                return -EINVAL;
@@ -2317,7 +2219,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                if (idx_value & 0x2) {
                        u64 offset;
                        /* DST is memory. */
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
                                return -EINVAL;
@@ -2505,7 +2407,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
 
 void r600_cs_legacy_init(void)
 {
-       r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
+       r600_nomm = 1;
 }
 
 /*