drm/amdgpu: factor out the AMDGPU_INFO_FW_VERSION case branch into amdgpu_firmware_info
authorHuang Rui <ray.huang@amd.com>
Sun, 12 Jun 2016 07:44:44 +0000 (15:44 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 7 Jul 2016 18:51:33 +0000 (14:51 -0400)
The new amdgpu_firmware_info function will be used on amdgpu firmware
version debugfs.

Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
include/uapi/drm/amdgpu_drm.h

index d851ea15059fe5ccd820d43ba725619ce7fcc97a..56c857f6e7ca78b93430e5c5e04bb2def213c8c9 100644 (file)
@@ -142,6 +142,65 @@ out:
        return r;
 }
 
+static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
+                               struct drm_amdgpu_query_fw *query_fw,
+                               struct amdgpu_device *adev)
+{
+       switch (query_fw->fw_type) {
+       case AMDGPU_INFO_FW_VCE:
+               fw_info->ver = adev->vce.fw_version;
+               fw_info->feature = adev->vce.fb_version;
+               break;
+       case AMDGPU_INFO_FW_UVD:
+               fw_info->ver = adev->uvd.fw_version;
+               fw_info->feature = 0;
+               break;
+       case AMDGPU_INFO_FW_GMC:
+               fw_info->ver = adev->mc.fw_version;
+               fw_info->feature = 0;
+               break;
+       case AMDGPU_INFO_FW_GFX_ME:
+               fw_info->ver = adev->gfx.me_fw_version;
+               fw_info->feature = adev->gfx.me_feature_version;
+               break;
+       case AMDGPU_INFO_FW_GFX_PFP:
+               fw_info->ver = adev->gfx.pfp_fw_version;
+               fw_info->feature = adev->gfx.pfp_feature_version;
+               break;
+       case AMDGPU_INFO_FW_GFX_CE:
+               fw_info->ver = adev->gfx.ce_fw_version;
+               fw_info->feature = adev->gfx.ce_feature_version;
+               break;
+       case AMDGPU_INFO_FW_GFX_RLC:
+               fw_info->ver = adev->gfx.rlc_fw_version;
+               fw_info->feature = adev->gfx.rlc_feature_version;
+               break;
+       case AMDGPU_INFO_FW_GFX_MEC:
+               if (query_fw->index == 0) {
+                       fw_info->ver = adev->gfx.mec_fw_version;
+                       fw_info->feature = adev->gfx.mec_feature_version;
+               } else if (query_fw->index == 1) {
+                       fw_info->ver = adev->gfx.mec2_fw_version;
+                       fw_info->feature = adev->gfx.mec2_feature_version;
+               } else
+                       return -EINVAL;
+               break;
+       case AMDGPU_INFO_FW_SMC:
+               fw_info->ver = adev->pm.fw_version;
+               fw_info->feature = 0;
+               break;
+       case AMDGPU_INFO_FW_SDMA:
+               if (query_fw->index >= adev->sdma.num_instances)
+                       return -EINVAL;
+               fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
+               fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
+               break;
+       default:
+               return -EINVAL;
+       }
+       return 0;
+}
+
 /*
  * Userspace get information ioctl
  */
@@ -292,63 +351,16 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
        case AMDGPU_INFO_FW_VERSION: {
                struct drm_amdgpu_info_firmware fw_info;
+               int ret;
 
                /* We only support one instance of each IP block right now. */
                if (info->query_fw.ip_instance != 0)
                        return -EINVAL;
 
-               switch (info->query_fw.fw_type) {
-               case AMDGPU_INFO_FW_VCE:
-                       fw_info.ver = adev->vce.fw_version;
-                       fw_info.feature = adev->vce.fb_version;
-                       break;
-               case AMDGPU_INFO_FW_UVD:
-                       fw_info.ver = adev->uvd.fw_version;
-                       fw_info.feature = 0;
-                       break;
-               case AMDGPU_INFO_FW_GMC:
-                       fw_info.ver = adev->mc.fw_version;
-                       fw_info.feature = 0;
-                       break;
-               case AMDGPU_INFO_FW_GFX_ME:
-                       fw_info.ver = adev->gfx.me_fw_version;
-                       fw_info.feature = adev->gfx.me_feature_version;
-                       break;
-               case AMDGPU_INFO_FW_GFX_PFP:
-                       fw_info.ver = adev->gfx.pfp_fw_version;
-                       fw_info.feature = adev->gfx.pfp_feature_version;
-                       break;
-               case AMDGPU_INFO_FW_GFX_CE:
-                       fw_info.ver = adev->gfx.ce_fw_version;
-                       fw_info.feature = adev->gfx.ce_feature_version;
-                       break;
-               case AMDGPU_INFO_FW_GFX_RLC:
-                       fw_info.ver = adev->gfx.rlc_fw_version;
-                       fw_info.feature = adev->gfx.rlc_feature_version;
-                       break;
-               case AMDGPU_INFO_FW_GFX_MEC:
-                       if (info->query_fw.index == 0) {
-                               fw_info.ver = adev->gfx.mec_fw_version;
-                               fw_info.feature = adev->gfx.mec_feature_version;
-                       } else if (info->query_fw.index == 1) {
-                               fw_info.ver = adev->gfx.mec2_fw_version;
-                               fw_info.feature = adev->gfx.mec2_feature_version;
-                       } else
-                               return -EINVAL;
-                       break;
-               case AMDGPU_INFO_FW_SMC:
-                       fw_info.ver = adev->pm.fw_version;
-                       fw_info.feature = 0;
-                       break;
-               case AMDGPU_INFO_FW_SDMA:
-                       if (info->query_fw.index >= adev->sdma.num_instances)
-                               return -EINVAL;
-                       fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version;
-                       fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version;
-                       break;
-               default:
-                       return -EINVAL;
-               }
+               ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
+               if (ret)
+                       return ret;
+
                return copy_to_user(out, &fw_info,
                                    min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
        }
index cdecf87576e890f48c7e93830c920fa33ff9b85e..462246aa200e1db1890de7d6640c81e859da250d 100644 (file)
@@ -487,6 +487,22 @@ struct drm_amdgpu_cs_chunk_data {
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
 #define AMDGPU_INFO_MMR_SH_INDEX_MASK  0xff
 
+struct drm_amdgpu_query_fw {
+       /** AMDGPU_INFO_FW_* */
+       __u32 fw_type;
+       /**
+        * Index of the IP if there are more IPs of
+        * the same type.
+        */
+       __u32 ip_instance;
+       /**
+        * Index of the engine. Whether this is used depends
+        * on the firmware type. (e.g. MEC, SDMA)
+        */
+       __u32 index;
+       __u32 _pad;
+};
+
 /* Input structure for the INFO ioctl */
 struct drm_amdgpu_info {
        /* Where the return value will be stored */
@@ -522,21 +538,7 @@ struct drm_amdgpu_info {
                        __u32 flags;
                } read_mmr_reg;
 
-               struct {
-                       /** AMDGPU_INFO_FW_* */
-                       __u32 fw_type;
-                       /**
-                        * Index of the IP if there are more IPs of
-                        * the same type.
-                        */
-                       __u32 ip_instance;
-                       /**
-                        * Index of the engine. Whether this is used depends
-                        * on the firmware type. (e.g. MEC, SDMA)
-                        */
-                       __u32 index;
-                       __u32 _pad;
-               } query_fw;
+               struct drm_amdgpu_query_fw query_fw;
        };
 };