The default adc_clock for the zl10353 is different from what was originally
thought to be the case and the TRL nominal rate formula was incorrect as a
result. Use a better (and hopefully now correct) formula.
Signed-off-by: Chris Pascoe <c.pascoe@itee.uq.edu.au>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
enum fe_bandwidth bandwidth,
u16 *nominal_rate)
{
enum fe_bandwidth bandwidth,
u16 *nominal_rate)
{
- u32 adc_clock = 22528; /* 20.480 MHz on the board(!?) */
+ u32 adc_clock = 45056; /* 45.056 MHz */
u8 bw;
struct zl10353_state *state = fe->demodulator_priv;
u8 bw;
struct zl10353_state *state = fe->demodulator_priv;
- *nominal_rate = (64 * bw * (1<<16) / (7 * 8) * 4000 / adc_clock + 2) / 4;
+ *nominal_rate = (bw * (1 << 23) / 7 * 125 + adc_clock / 2) / adc_clock;
dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
__FUNCTION__, bw, adc_clock, *nominal_rate);
dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
__FUNCTION__, bw, adc_clock, *nominal_rate);
u8 demod_address;
/* frequencies in kHz */
u8 demod_address;
/* frequencies in kHz */
- int adc_clock; // default: 22528
+ int adc_clock; /* default: 45056 */
/* set if no pll is connected to the secondary i2c bus */
int no_tuner;
/* set if no pll is connected to the secondary i2c bus */
int no_tuner;