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(parent: f3c67fd) | patch
drm/i915/chv: Add display interrupt registers bits for Cherryview
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 9 Apr 2014 10:28:06 +0000 (13:28 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 6 May 2014 19:17:17 +0000 (21:17 +0200)
commitfac12f6cdcb25cac8f28818a8f9adb079575f9a0
treea21ec530e5d4a88658619d66ddb23e545aa8a971tree | snapshot (tar.gz zip)
parentf3c67fdd6112a6af9505f3af782e145024aa9643commit | diff
drm/i915/chv: Add display interrupt registers bits for Cherryview

v2: Rebase on top of Ben's GT interrupt shuffling.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history