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clk: samsung: exynos7: Fix CMU TOPC block clock
authorAlim Akhtar <alim.akhtar@samsung.com>
Wed, 26 Aug 2015 03:30:41 +0000 (09:00 +0530)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Tue, 15 Sep 2015 08:58:10 +0000 (10:58 +0200)
commitfa9f3a526459ef33f1ca54aad231c5a23071f37f
tree8bfa7e168b46877b1d4120c57d6ea910fa003262tree | snapshot (tar.gz zip)
parent6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357fcommit | diff
clk: samsung: exynos7: Fix CMU TOPC block clock

Corrects the bit width of DIV_TOPC3 register.
These are wrongly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos7.c diff | blob | blame | history