drm/i915: Changes related to the sequence port no for
authorGaurav K Singh <gaurav.k.singh@intel.com>
Wed, 10 Dec 2014 16:37:40 +0000 (22:07 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 15 Dec 2014 08:54:22 +0000 (09:54 +0100)
commitf915084edc5aad351d6a4675b0bcdded9a00090d
tree41721364e029a291f4b9c2e791fe48c7edb2ef01
parent5f77eeb05c9ee1de03fbe695b41362aae401726a
drm/i915: Changes related to the sequence port no for

From now on for both DSI Ports A & C, the seq_port value has been
set to 0. seq_port value is parsed from Sequence block#53 of VBT.
So, for packets that needs to be read/write for DSI single link on
Port A and Port C will now be based on the DVO port from VBT block 2,
instead of seq_port.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c