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MIPS: Add register definitions for VZ ASE registers
authorJames Hogan <james.hogan@imgtec.com>
Wed, 11 May 2016 14:50:28 +0000 (15:50 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 13 May 2016 13:30:25 +0000 (15:30 +0200)
commitf913e9ea3946902f5443e703d70d5daf90f4498a
treea0df85b3261e5f00e3f8b2c51fa98358efc3d784tree | snapshot (tar.gz zip)
parent9e575f753576d85e83ae0afc27eca9708259a797commit | diff
MIPS: Add register definitions for VZ ASE registers

Add various register definitions to <asm/mipsregs.h> for the coprocessor
zero registers in the VZ ASE, namely CP0_GuestCtl0, CP0_GuestCtl0Ext,
CP0_GuestCtl1, CP0_GuestCtl2, CP0_GuestCtl3, and CP0_GTOffset.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13228/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mipsregs.h diff | blob | blame | history
Motorola kernel-slsi