clk: rockchip: Make uartpll a child of the gpll on rk3036
authorHeiko Stuebner <heiko@sntech.de>
Wed, 1 Mar 2017 21:00:42 +0000 (22:00 +0100)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 7 Mar 2017 13:54:50 +0000 (05:54 -0800)
commitf8ba2d68e54fbca340ad0fce97397291ba9637bc
tree843c766da16133f7de08910d8307a58a567ce609
parent9b1b23f03abdd25ffde8bbfe5824b89bc0448c28
clk: rockchip: Make uartpll a child of the gpll on rk3036

The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.

This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/rockchip/clk-rk3036.c