clk: renesas: r8a7795: Correct lvds clock parent
authorGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 10 Jun 2016 07:36:44 +0000 (09:36 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 21 Jun 2016 07:21:05 +0000 (09:21 +0200)
commitf7bb887fb898307dd575179303b710d933f242ea
treeb190bdf332f5ce150e1e9ced5b082aaf149ca670
parenta20956804220951196671ed5455d085927d6a754
clk: renesas: r8a7795: Correct lvds clock parent

According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.

Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
drivers/clk/renesas/r8a7795-cpg-mssr.c