drm/fsl-dcu: fix register initialization
authorStefan Agner <stefan@agner.ch>
Fri, 15 Jan 2016 01:24:29 +0000 (17:24 -0800)
committerStefan Agner <stefan@agner.ch>
Fri, 26 Feb 2016 00:13:16 +0000 (16:13 -0800)
commitf76b9873d7db0afb51f2df389a99284ef484b86f
treee4258bfb255fd5d35c430c8508548c10f83ea2d8
parent4bc390c6337b6c73e0b44895e0ade7212f2815bf
drm/fsl-dcu: fix register initialization

The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for
Vybrid) whereas the register enumeration start from 1 (1-10 for
LS1021a and 1-9 for Vybrid). The loop started off from 0 for both
iterations and initialized the number of layers inclusive, which
is one layer too many.

All extensively written registers seem to be unassigned, it seems
that the write to those registers did not do any harm in practice.

Signed-off-by: Stefan Agner <stefan@agner.ch>
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c