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(parent: 97fd4d5) | patch
drm/i915/chv: Don't do group access reads from TX lanes either
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 9 Apr 2014 10:29:03 +0000 (13:29 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 20 May 2014 13:52:38 +0000 (15:52 +0200)
commitf72df8dbe2211cf2b70e54f8e9408b889fa56974
treefc8900ccbbd5ab19e78a79ea7edd426d4ede33f0tree | snapshot (tar.gz zip)
parent97fd4d5c81af7976b4ec9971a93bf3c361066c65commit | diff
drm/i915/chv: Don't do group access reads from TX lanes either

Like PCS, TX group reads return 0xffffffff. So we need to target each
lane separately if we want to use RMW cycles to update the registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history
drivers/gpu/drm/i915/intel_dp.c diff | blob | blame | history
drivers/gpu/drm/i915/intel_hdmi.c diff | blob | blame | history