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(parent: 24af6c4) | patch
arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills
authorFlorian Fainelli <f.fainelli@gmail.com>
Thu, 20 Apr 2017 19:05:45 +0000 (12:05 -0700)
committerCatalin Marinas <catalin.marinas@arm.com>
Fri, 28 Apr 2017 14:23:36 +0000 (15:23 +0100)
commitf5337346cd8fe1b105f319b4b7fb06fe25c54480
tree44a7b3559a6c24f2f7e4dbe731251b0b652e3131tree | snapshot (tar.gz zip)
parent24af6c4e4e0f6e9803bec8dca0f7748afbb2bbf0commit | diff
arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills

Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/kernel/perf_event.c diff | blob | blame | history