drm/i915/glk: Add DSI PLL divider range for glk
authorDeepak M <m.deepak@intel.com>
Fri, 17 Feb 2017 12:43:32 +0000 (18:13 +0530)
committerJani Nikula <jani.nikula@intel.com>
Tue, 28 Feb 2017 09:46:50 +0000 (11:46 +0200)
commitf340c2ff5ebdd213682fe8b9a14838878cd0ff01
tree0ceb20e57640f966f452d2b7b7ba77347736a719
parentb426f985158d9a723ab195258748c0c5e0793a52
drm/i915/glk: Add DSI PLL divider range for glk

PLL divider range for GLK is different than that of
BXT, hence adding the GLK range check in this patch.

v2: Code restructure using min and max ratio variables (Ander)
v3: Code changes to avoid "maybe-uninitialized" warning (Jani)

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-5-git-send-email-madhav.chauhan@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_dsi_pll.c