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(parent: 7a58bad) | patch
drm/i915: WaRsDisableCoarsePowerGating
authorSagar Arun Kamble <sagar.a.kamble@intel.com>
Sat, 12 Sep 2015 04:47:51 +0000 (10:17 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 23 Sep 2015 08:48:49 +0000 (10:48 +0200)
commitf2d2fe95072acd5404f8051b8bf1195c61a47fb5
treeed67b30bad8284560b65a478fbab2bb9058bb838tree | snapshot (tar.gz zip)
parent7a58bad0e63295dfa803973efcebc80cb730c7bdcommit | diff
drm/i915: WaRsDisableCoarsePowerGating

WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.

v2: Added GT3/GT4 Check.

Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Alex Dai <yu.dai@intel.com>
[danvet: Align continuation properly.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c diff | blob | blame | history
Motorola kernel-slsi