MIPS: Loongson1B: Some fixes/updates for LS1B
authorKelvin Cheung <keguang.zhang@gmail.com>
Fri, 10 Oct 2014 03:40:01 +0000 (11:40 +0800)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 24 Nov 2014 06:45:09 +0000 (07:45 +0100)
commitf29ad10de6c345c8ae4cb33a99ba8ff29bdcd751
treeac377224cfbe7b116ad9f68deb85fd9dc84f93c4
parent813c14108d0f5bbddc125fb7a6a0819fcdcf61e2
MIPS: Loongson1B: Some fixes/updates for LS1B

- Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data.
   (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1)
 - Add GMAC1 support and setup MUX in terms of PHY mode.
 - Add CPUFreq support.
 - Add MUX Register Definitions.
 - Add PWM Register Definitions.
 - Update clock register bitfields according to the latest spec.
 - Update clock related stuff.

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8024/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/Kconfig
arch/mips/include/asm/mach-loongson1/cpufreq.h [new file with mode: 0644]
arch/mips/include/asm/mach-loongson1/loongson1.h
arch/mips/include/asm/mach-loongson1/platform.h
arch/mips/include/asm/mach-loongson1/regs-clk.h
arch/mips/include/asm/mach-loongson1/regs-mux.h [new file with mode: 0644]
arch/mips/include/asm/mach-loongson1/regs-pwm.h [new file with mode: 0644]
arch/mips/loongson1/common/platform.c
arch/mips/loongson1/ls1b/board.c