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(parent: 3e1a80f) | patch
[ARM] Always mark ARMv6 PTWs outer cacheable
authorRussell King <rmk@dyn-67.arm.linux.org.uk>
Thu, 8 Feb 2007 20:46:20 +0000 (20:46 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 8 Feb 2007 20:46:20 +0000 (20:46 +0000)
commitf2131d348f0bd252801f641018a90d59c987ce48
tree536676e6189742b0c268c5bfcc3f55dd7f5b00c3tree | snapshot (tar.gz zip)
parent3e1a80f11f89f318e892694b501735abb51ef626commit | diff
[ARM] Always mark ARMv6 PTWs outer cacheable

Other platforms other than SMP may have an outer cache.  For these, we
also need to mark the page table walks outer cacheable.  Since marking
the walks always outer cacheable apparantly has no side effects, we
might as well always mark them so.

However, we continue to only mark PTWs shared if we have SMP enabled.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/proc-v6.S diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)