drm/i915: Enable register whitelist checks
authorBrad Volkin <bradley.d.volkin@intel.com>
Tue, 18 Feb 2014 18:15:52 +0000 (10:15 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 1 Apr 2014 20:58:12 +0000 (22:58 +0200)
commitf0a346bdafaf6fc4a51df9ddf1548fd888f860d8
treed0d1fd5e54de83256b33a0ee1476fd76a1189f81
parent220375aa12c95744cd71d236f7c1ee39d277b6ed
drm/i915: Enable register whitelist checks

MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
commands allow userspace access to registers. Only certain registers
should be allowed for such access, so enable checking for those commands.
Each ring gets its own register whitelist.

MI_LOAD_REGISTER_REG on HSW also allows register access but is currently
unused by userspace components. Leave it rejected.

PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain
bits being set. Reject those as well.

v2: trailing commas, rebased

OTC-Tracker: AXIA-4631
Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_cmd_parser.c
drivers/gpu/drm/i915/i915_reg.h